Abstract: Embodiments of the invention generally fall into the category of activated thymulin synthesis and applications thereof. Embodiments, delivered orally or parenterally, are used to treat malignancies and immune system dysfunctions by activating cytotoxic T cells, increasing the generation of T helper 1 cells and/or boosting the production of interleukin 2.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.

Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.

Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.

Abstract: Integrated circuits include fins including an upper/channel region and a lower/sub-channel region, the lower region having a first chemical composition and opposing sidewalls adjacent to an insulator material, and the upper region having a second chemical composition. A first width indicates the distance between the opposing sidewalls of the lower region at a first location is at least 1 nm wider than a second width indicating the distance between the opposing sidewalls of the upper region at a second location, the first location being within 10 nm of the second location (or otherwise relatively close to one another). The first chemical composition is distinct from the second chemical composition and includes a surface chemical composition at an outer surface of the opposing sidewalls of the lower region and a bulk chemical composition therebetween, the surface chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, and sulfur.

Abstract: Techniques are disclosed for forming diverse transistor channel materials enabled by a thin, inverse-graded, germanium (Ge)-based layer. The thin, inverse-graded, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the inverse grading of the Ge concentration in the layer, where the Ge concentration is relatively greatest near the substrate and relatively lowest near the overlying channel material layer. In addition to the inverse-graded Ge concentration, the Ge-based layer may be characterized by the nucleation, and predominant containment, of defects at/near the interface between the substrate and the Ge-based layer.

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

Abstract: Techniques and mechanisms for exchanging information between a solid state drive (SSD) and a write-in-place non-volatile memory via a host device. In an embodiment, access control information defines state of the SSD, where the access control information determines and/or is based on an access by the host device to other non-volatile memory of the SSD. The access control information includes address conversion information defining a correspondence of a logical address with a physical address for a location of the other non-volatile memory of the SSD. At least some of the access control information is stored by the SSD to the write-in-place non-volatile memory for later retrieval by the SSD. In another embodiment, the SSD signals that a commit operation is to be performed to flush any cached or buffered access control information into the write-in-place non-volatile memory.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the STI is doped with an n-type impurity, in regions of the STI adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the STI region is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the thickness of the doped STI region may range between 10 and 100 nanometers.