Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

Abstract: Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.

Abstract: SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.

Abstract: IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nanoribbon) of one or more semiconductor materials extending between a first side (e.g., a back side) and an opposing second side (e.g., a front side) of a substrate. The first S/D region of the transistor may be provided at the first side of the substrate, while the second S/D region of the transistor may be provided at the second side, with the channel region of the transistor being the portion of the elongated structure between the first and second S/D regions. Implementing various logic circuits using vertical transistors with backside S/D regions may provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

Abstract: Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.

Abstract: IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

Abstract: Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.

Abstract: IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

Abstract: IC devices implementing 2T memory cells with source-drain coupling in one transistor, and related assemblies and methods, are disclosed herein. In particular, 2T memory cells presented herein use first and second transistors arranged so that source and drain terminals of the second transistor are coupled to one another. A memory state may be represented by charge indicative of the bit value stored in the second transistor, while the first transistor may serve as a switch to control access to the second transistor. 2T memory cells with source-drain coupling in one transistor provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

Abstract: IC devices with transistors having angled gates, and related assemblies and methods, are disclosed herein. A transistor is referred to as having an “angled gate” if an angle between a projection of the gate of the transistor onto a plane of a support structure (e.g., a die) over which the transistor is implemented and an analogous projection of a longitudinal axis of an elongated structure (e.g., a fin or a nanoribbon having one or more semiconductor materials) based on which the transistor is built is between 10 degrees and 80 degrees. Transistors having angled gates provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor’s source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor’s channel region and extends downward into a recess that exposes the lower transistor’s source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor’s source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with selective silicide contacts thereon are described. In an example, an integrated circuit structure includes a plurality of stacks of nanowires. A plurality of epitaxial source or drain structures is around ends of corresponding ones of the stacks of nanowires. A silicide layer is on an entirety of a top surface of the plurality of epitaxial source or drain structures. A conductive trench contact is on the silicide layer. A dielectric layer is vertically intervening between a portion of the conductive trench contact and the silicide layer.

Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include thick hysteretic elements (i.e., hysteretic elements having a thickness of at least 10-15 nanometers, e.g., between 55 and 100 nanometers), and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate insulator having a thick hysteretic element and an interface layer, where the thick hysteretic element is between the interface layer and a gate electrode material, and the interface layer is between the thick hysteretic element and a channel material of a transistor. The interface layer may be a dielectric material with an effective dielectric constant of at least 20 and/or be a dielectric material that is thinner than about 3 nanometers. Such an interface layer may help improve gate control and allow use of thick hysteretic elements while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Reducing transistor dimensions at the gate allows keeping the footprint of the transistor relatively small and comparable to what could be achieved implementing a transistor with a shorter gate length while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower.