Patents by Inventor Anand Srinivasan

Anand Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070224753
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Application
    Filed: June 1, 2007
    Publication date: September 27, 2007
    Inventors: Sanh Tang, Robert Burke, Anand Srinivasan
  • Patent number: 7241655
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: July 10, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Robert J. Burke, Anand Srinivasan
  • Publication number: 20070143640
    Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventors: Brad Simeral, David Reed, Dmitry Vyshetsky, Roman Surgutchick, Robert Chapman, Joshua Titus, Anand Srinivasan, Hari Krishnan
  • Patent number: 7187652
    Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: March 6, 2007
    Assignee: Tropic Networks Inc.
    Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
  • Publication number: 20070048943
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Application
    Filed: May 23, 2006
    Publication date: March 1, 2007
    Inventors: Sanh Tang, Robert Burke, Anand Srinivasan
  • Publication number: 20060256937
    Abstract: A method for discovering relationships among elements of a transactional conversation includes tagging a transcribed representation of the conversation to identify elements of the conversation and structuring the tagged conversation according to a specified format to produce a structured, tagged representation of the conversation. A set of structured, tagged conversation representations is then analyzed to discover a relationship between a first conversation element and a second conversation element. Tagging the conversation may include evaluating a portion of the conversation, assigning the portion a message type, and assigning a data value to an attribute defined by the message type. The message type may be defined by a conversation policy, wherein the conversation policy identifies conversation elements including conversation states and message types that transition the conversation among the conversation states.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 16, 2006
    Inventors: Paul Foreman, David Greene, Philip Light, Razvan Loghin, Anand Srinivasan
  • Publication number: 20060253524
    Abstract: A method and apparatus for creating new representations of a conversational policy or conversation are shown. The conversational policy or a specific conversation can be displayed in a tabular form, which emphasizes order and timing. Representing the policy as a ‘filmstrip’ or series of interactions can make writing the conversational policy more understandable.
    Type: Application
    Filed: May 5, 2005
    Publication date: November 9, 2006
    Inventors: Paul Foreman, David Greene, Philip Light, Razvan Loghin, Anand Srinivasan
  • Publication number: 20060253843
    Abstract: A method and apparatus for taking a visual or verbal representation of a conversational policy and translating the representation into an XML file. The XML file can then be output in one or more formats, such as code used in a policy, a Word version of the XML file, or a visual representation of the XML file.
    Type: Application
    Filed: May 5, 2005
    Publication date: November 9, 2006
    Inventors: Paul Foreman, David Greene, Philip Light, Razvan Loghin, Anand Srinivasan
  • Patent number: 7112531
    Abstract: Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide. The method is particularly useful for providing silicon oxide spacers with faceted surfaces.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Anand Srinivasan
  • Patent number: 7054987
    Abstract: A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transaction request would fill the resource beyond a current remaining capacity of the resource such that the execution of other pipelined transactions would become stalled, the bus interface generates a retry response so that the request is retried at a later time, permitting other transactions to proceed while the resource drains.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: May 30, 2006
    Assignee: Nvidia Corporation
    Inventors: David G. Reed, Brian K. Langendorf, Brad W. Simeral, Anand Srinivasan
  • Publication number: 20060046391
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 2, 2006
    Inventors: Sanh Tang, Robert Burke, Anand Srinivasan
  • Patent number: 6952051
    Abstract: An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: October 4, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Anand Srinivasan, Ravi Iyer
  • Patent number: 6933242
    Abstract: A substrate whose elemental constituents are selected from Groups III and V of the Periodic Table, is provided with pre-defined masked regions. Etching of the substrate comprising the steps of: a) forming a gas containing molecules having at least one methyl group (CH3) linked to nitrogen into a plasma; and b) etching the unmasked regions of the substrate by means of the plasma. For a substrate whose elemental constituents are selected from Groups II and VI of the Periodic Table, the plasma etching gas used is trimethylamine. Since the methyl compound of nitrogen has a lower bond energy than for hydrocarbon mixtures, free methyl radicals are easier to obtain and the gas is more efficient as a methyl source. In addition, compared with hydrocarbon mixtures, reduced polymer formation can be expected due to preferential formation of methyl radicals over polymer-generating hydrocarbon radicals because of the lower bond energy for the former.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: August 23, 2005
    Assignee: Surface Technology Systems PLC
    Inventors: Anand Srinivasan, Carl-Fredrik Carlstrom, Gunnar Landgren
  • Patent number: 6925061
    Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: August 2, 2005
    Assignee: Tropic Network Inc.
    Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
  • Publication number: 20050153470
    Abstract: A method to obtain contamination free surfaces of a material chosen from the group comprising GaAs, GaAlAs, InGaAs, InGaAsP and InGaAs at crystal mirror facets for GaAs based laser cavities. The crystal mirrors facets are cleaved out exposed to an ambient atmosphere containing a material from the group comprising air, dry air, or dry nitrogen ambients. Any oxides and other foreign contaminants obtained during the ambient atmosphere exposure of the mirror facets are removed by dry etching in vacuum. Thereafter, a native nitride layer is grown on the mirror facets by treating them with nitrogen.
    Type: Application
    Filed: November 2, 2004
    Publication date: July 14, 2005
    Inventors: L. Lindstrom, N. Blixt, Svante Soderholm, Anand Srinivasan, Carl-Fredrik Carlstorm
  • Patent number: 6889338
    Abstract: A fault-tolerant server group operating in client-server distributed dynamic network system environment includes a master server which receives a request sent by a client. The fault-tolerant server group includes the master server and at least one back-up server. The master server communicates with both the client and the back-up servers. Each server in the fault-tolerant server group, including the master server and the back-up servers, has an election mechanism, enabling the fault-tolerant server group to elect a new master server when the master server fails. During the election, some of the election mechanisms are triggered at different times. The fault-tolerant server group processes the request from the client to generate processing result. The processing result is sent from the master server to the client.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: May 3, 2005
    Assignee: Nortel Networks Limited
    Inventors: Anand Srinivasan, Pramod Dhakal
  • Patent number: 6841463
    Abstract: An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: January 11, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Anand Srinivasan, Ravi Iyer
  • Patent number: 6812152
    Abstract: A method to obtain contamination free surfaces of a material chosen from the group comprising GaAs, GaAlAs, InGaAs, InGaAsP and InGaAs at crystal mirror facets for GaAs based laser cavities. The crystal mirrors facets are cleaved out exposed to an ambient atmosphere containing a material from the group comprising air, dry air, or dry nitrogen ambients. Any oxides and other foreign contaminants obtained during the ambient atmosphere exposure of the mirror facets are removed by dry etching in vacuum. Thereafter, a native nitride layer is grown on the mirror facets by treating them with nitrogen.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: November 2, 2004
    Assignee: Comlase AB
    Inventors: L. Karsten V. Lindström, N. Peter Blixt, Svante H. Söderholm, Anand Srinivasan, Carl-Fredrik Carlström
  • Patent number: 6803605
    Abstract: The invention relates to a method using dry etching to obtain contamination free surfaces on of a material chosen from the group comprising GaAs, GaAlAs, InGaAsP, and InGaAs to obtain nitride layers on arbitrary structures on GaAs based lasers, and a GaAs based laser manufactured in accordance with the method. The laser surface is provided with a mask masking away parts of its surface to be prevented from dry etching. The laser is then placed in vacuum. Dry etching is then performed using a substance chosen from the group containing: chemically reactive gases, inert gases, a mixture between chemically reactive gases and inert gases. A native nitride layer is created using plasma containing nitrogen. A protective layer and/or a mirror coating is added.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: October 12, 2004
    Assignee: Comlase AB
    Inventors: L. Karsten V. Lindstrom, N. Peter Blixt, Svante H. Soderholm, Lauerant Krummenacher, Christofer Silvenius, Anand Srinivasan, Carl-Fredrik Carlstrom
  • Publication number: 20040185183
    Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si-F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
    Type: Application
    Filed: January 30, 2004
    Publication date: September 23, 2004
    Inventors: Anand Srinivasan, Gurtej Sandhu, Ravi Iyer