Patents by Inventor Anand Srinivasan

Anand Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6734111
    Abstract: The invention relates to a method using dry etching to obtain contamination free surfaces on of a material chosen from the group comprising GaAs, GaAlAs, InGaAsP, and InGaAs to obtain nitride layers on arbitrary structures on GaAs based lasers, and a GaAs based laser manufactured in accordance with the method. The laser surface is provided with a mask masking away parts of its surface to be prevented from dry etching. The laser is then placed in vacuum. Dry etching is then performed using a substance chosen from the group containing: chemically reactive gases, inert gases, a mixture between chemically reactive gases and inert gases. A native nitride layer is created using plasma containing nitrogen. A protective layer and/or a mirror coating is added.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: May 11, 2004
    Assignee: Comlase AB
    Inventors: L. Karsten V. Lindström, N. Peter Blixt, Svante H. Söderholm, Lauerent Krummenacher, Christofer Silvenius, Anand Srinivasan, Carl-Fredrik Carlström
  • Patent number: 6727190
    Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: April 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Gurtej Sandhu, Ravi Iyer
  • Publication number: 20030166988
    Abstract: A method for reducing dioxin levels from a sludge disposal process comprising: (a) adding a halogenation supressant to a composition containing dioxin precursors, (b) incinerating the composition containing dioxin precursors, thereby forming a gaseous medium, (c) reducing heat in the gaseous medium formed in step (b), (d) removing ash from the gaseous medium, (e) adding an adsorbent to the gaseous medium formed in step (d), and (f) removing acid gases and particulates from the gaseous medium formed in step (e).
    Type: Application
    Filed: March 14, 2001
    Publication date: September 4, 2003
    Inventors: Christopher A. Hazen, James I. Myers, Anand Srinivasan, Bernhard Wilhelm Vosteen
  • Publication number: 20030162346
    Abstract: Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide. The method is particularly useful for providing silicon oxide spacers with faceted surfaces.
    Type: Application
    Filed: March 3, 2003
    Publication date: August 28, 2003
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Anand Srinivasan
  • Publication number: 20030118024
    Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.
    Type: Application
    Filed: May 23, 2002
    Publication date: June 26, 2003
    Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
  • Publication number: 20030118027
    Abstract: A routing system and method are provided which use a composite cost in identifying routes. This allows a simple way of identifying the best route taking multiple metrics into account for each link simultaneously. The system allows for the inclusion of pruning constraints, and allows for various objectives such as bin packing or load balancing to be achieved.
    Type: Application
    Filed: December 26, 2001
    Publication date: June 26, 2003
    Inventors: Byoung-Joon Lee, Sudhakar Ganti, Anand Srinivasan, Walter Joseph Carpini, Udo Mircea Neustadter, Cuong Tu Dang, Vincent Chi Chiu Wong
  • Patent number: 6537910
    Abstract: A metal suicide film and method of forming the same are provided. The method comprises depositing metal silicide layers onto a substrate assembly with alternating layers of silicon. The resulting metal silicide film has a disrupted grain structure and smaller grain sizes than prior art films of the same thickness, which increases the resistance of the material to stress cracks in subsequent thermal processing and reduces the overall residual stress of the material.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: March 25, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Robert Burke, Farrell Good, Anand Srinivasan
  • Patent number: 6534409
    Abstract: Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide. The method is particularly useful for providing silicon oxide spacers with faceted surfaces.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: March 18, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Anand Srinivasan
  • Publication number: 20030047739
    Abstract: The invention relates to a method using dry etching to obtain contamination free surfaces on of a material chosen from the group comprising GaAs, GaAlAs, InGaAsP, and InGaAs to obtain nitride layers on arbitrary structures on GaAs based lasers, and a GaAs based laser manufactured in accordance with the method. The laser surface is provided with a mask masking away parts of its surface to be prevented from dry etching. The laser is then placed in vacuum. Dry etching is then performed using a substance chosen from the group containing: chemically reactive gases, inert gases, a mixture between chemically reactive gases and inert gases. A native nitride layer is created using plasma containing nitrogen. A protective layer and/or a mirror coating is added.
    Type: Application
    Filed: August 15, 2002
    Publication date: March 13, 2003
    Inventors: L. Karsten V. Lindstrom, N. Peter Blixt, Svante H. Soderholm, Lauerent Krummenacher, Christofer Silvenius, Anand Srinivasan, Carl-Fredrik Carlstrom
  • Publication number: 20030037284
    Abstract: A fault-tolerant server group operating in client-server distributed dynamic network system environment includes a master server and at least one back-up server. The master server registers its mastership in a name server. The master server communicates with the client and the back-up servers. Each server in the fault-tolerant server group has a self-monitoring mechanism, ensuring a consistent mastership. The fault-tolerant server group processes the request from the client to generate a processing result. The processing result is sent from the master server to the client.
    Type: Application
    Filed: September 27, 2001
    Publication date: February 20, 2003
    Inventors: Anand Srinivasan, Pramod Dhakal
  • Publication number: 20030037283
    Abstract: A fault-tolerant server group operating in client-server distributed dynamic network system environment includes a master server which receives a request sent by a client. The fault-tolerant server group includes the master server and at least one back-up server. The master server communicates with both the client and the back-up servers. Each server in the fault-tolerant server group, including the master server and the back-up servers, has an election mechanism, enabling the fault-tolerant server group to elect a new master server when the master server fails. During the election, some of the election mechanisms are triggered at different times. The fault-tolerant server group processes the request from the client to generate processing result. The processing result is sent from the master server to the client.
    Type: Application
    Filed: September 25, 2001
    Publication date: February 20, 2003
    Inventors: Anand Srinivasan, Pramod Dhakal
  • Publication number: 20030029836
    Abstract: A method to obtain contamination free surfaces of a material chosen from the group comprising GaAs, GaAlAs, InGaAs, InGaAsP and InGaAs at crystal mirror facets for GaAs based laser cavities. The crystal mirrors facets are cleaved out exposed to an ambient atmosphere containing a material from the group comprising air, dry air, or dry nitrogen ambients. Any oxides and other foreign contaminants obtained during the ambient atmosphere exposure of the mirror facets are removed by dry etching in vacuum. Thereafter, a native nitride layer is grown on the mirror facets by treating them with nitrogen.
    Type: Application
    Filed: August 9, 2001
    Publication date: February 13, 2003
    Inventors: L. Karsten V. Lindstrom, N. Peter Blixt, Svante H. Soderholm, Anand Srinivasan, Carl-Fredrik Carlstrom
  • Publication number: 20030032297
    Abstract: The invention relates to a method using dry etching to obtain contamination free surfaces on of a material chosen from the group comprising GaAs, GaAlAs, InGaAsP, and InGaAs to obtain nitride layers on arbitrary structures on GaAs based lasers, and a GaAs based laser manufactured in accordance with the method. The laser surface is provided with a mask masking away parts of its surface to be prevented from dry etching. The laser is then placed in vacuum. Dry etching is then performed using a substance chosen from the group containing: chemically reactive gases, inert gases, a mixture between chemically reactive gases and inert gases. A native nitride layer is created using plasma containing nitrogen. A protective layer and/or a mirror coating is added.
    Type: Application
    Filed: August 9, 2001
    Publication date: February 13, 2003
    Inventors: L. Karsten V. Lindstrom, N. Peter Blixt, Svante H. Soderholm, Lauerent Krummenacher, Christofer Silvenius, Anand Srinivasan, Carl-Fredrik Carlstrom
  • Patent number: 6509627
    Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: January 21, 2003
    Assignee: Micro Technology, Inc.
    Inventor: Anand Srinivasan
  • Patent number: 6499425
    Abstract: In a plasma processing apparatus, a showerhead is provided that allows for selective ionization of one or more process gasses within the showerhead. The showerhead allows the gasses to react after they exit the showerhead. As a result, a greater volume of materials are. available for deposition on a wafer surface during a chemical vapor deposition process than would be available in a process that remotely generates plasma. In addition, less damage is done to the wafer that would be done in a process that generates plasma next to the wafer.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: December 31, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Sujit Sharan, Anand Srinivasan
  • Patent number: 6472321
    Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions herein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: October 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Sujit Sharon, Raj Narasimhan
  • Patent number: 6429071
    Abstract: Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: August 6, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Sujit Sharan, Thomas A. Figura, Anand Srinivasan, Gurtej S. Sandhu
  • Patent number: 6423626
    Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Gurtej Sandhu, Sujit Sharan
  • Publication number: 20020091762
    Abstract: Systems and methods for displaying real time media broadcasts with pages of related information. The systems and methods allow a user to interact with related online information while simultaneously viewing a video presentation or listening to an audio presentation. A client application executing on a client system processes a streaming data signal and displays an associated real time media presentation, live or archived, on one portion of a display. Reference data pushed to the client application in the streaming data signal identifies pages of related information. The client application retrieves the pages, e.g., via HTTP requests, and displays the pages in a data frame on a second portion of the display. The pages can be created in advance of the media presentation, and when retrieved and displayed, include current information related to the subject matter of the media presentation. Information included in the pages can include links to other related information.
    Type: Application
    Filed: March 7, 2001
    Publication date: July 11, 2002
    Applicant: Yahoo! Inc.
    Inventors: Henry H. Sohn, Ronald Jacoby, Brian Bushman, Anand Srinivasan, Dean Burris, Justin Madison, Steve Linowes, Johnny J. Speaks
  • Publication number: 20020058413
    Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions therein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.
    Type: Application
    Filed: January 15, 2002
    Publication date: May 16, 2002
    Inventors: Anand Srinivasan, Sujit Sharon, Raj Narasimhan