Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions therein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.

Abstract: An authoring system for interactive video has two or more authoring stations for providing authored metadata to be related to a main video data stream and a multiplexer for relating authored metadata from the authoring sources to the main video data stream. The authoring stations annotate created metadata with presentation time stamps (PTS) from the main video stream, and the multiplexer relates the metadata to the main video stream by the PTS signatures. In analog streams PTS may be created and integrated. In some embodiments there may be multiple and cascaded systems, and some sources may be stored sources. Various methods are disclosed for monitoring and compensating time differences among sources to ensure time coordination in end product. In different embodiments transport of metadata to an end user station is provided by Internet streaming, VBI insertion or by Internet downloading.

Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: Methods and apparatus for depositing films on semiconductor wafers in chemical vapor deposition processes employing a catalyst to provide one or more activated gases to reduce the surface temperature of the semiconductor wafer needed to form the film thereon. The activated gas precursors can include hydrogen or hydrogen-bearing gases. The catalysts can be selected from ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, mercury, rhenium, copper, tungsten, and combinations thereof.

Abstract: An authoring system for interactive video has two or more authoring stations for providing authored metadata to be related to a main video data stream and a multiplexer for relating authored metadata from the authoring sources to the main video data stream. The authoring stations annotate created metadata with presentation time stamps (PTS) from the main video stream, and the multiplexer relates the metadata to the main video stream by the PTS signatures. In analog streams PTS may be created and integrated. In some embodiments there may be multiple and cascaded systems, and some sources may be stored sources. Various methods are disclosed for monitoring and compensating time differences among sources to ensure time coordination in end product. In different embodiments transport of metadata to an end user station is provided by Internet streaming, VBI insertion or by Internet downloading.

Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide. The method is particularly useful for providing silicon oxide spacers with faceted surfaces.

Abstract: A metal silicide film and method of forming the same are provided. The method comprises depositing metal silicide layers onto a substrate assembly with alternating layers of silicon. The resulting metal silicide film has a disrupted grain structure and smaller grain sizes than prior art films of the same thickness, which increases the resistance of the material to stress cracks in subsequent thermal processing and reduces the overall residual stress of the material.

Abstract: Methods and apparatus for depositing films on semiconductor wafers in chemical vapor deposition processes employing a catalyst to provide one or more activated gases to reduce the surface temperature of the semiconductor wafer needed to form the film thereon. The activated gas precursors can include hydrogen or hydrogen-bearing gases. The catalysts can be selected from ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, mercury, rhenium, copper, tungsten, and combinations thereof.

Abstract: An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

Abstract: An interlevel dielectric structure includes forming first and second dielectric layers between which are located lines of a conductive material that are also formed with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.

Abstract: Methods and apparatus for depositing films on semiconductor wafers in chemical vapor deposition processes employing a catalyst to provide one or more activated gases to reduce the surface temperature of the semiconductor wafer needed to form the film thereon. The activated gas precursors can include hydrogen or hydrogen-bearing gases. The catalysts can be selected from ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, mercury, rhenium, copper, tungsten, and combinations thereof.

Abstract: Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF.sub.3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

Abstract: An internal combustion engine includes a precombustion member which has a number of first ignition orifices defined therein. The precombustion member further has a precombustion chamber defined therein. The precombustion member is positioned relative to the head of the engine such that the precombustion chamber is in fluid communication with the engine's main combustion chamber via the first ignition orifices. The internal combustion engine further has a spark plug for igniting a gaseous fuel. The spark plug includes an encapsulating member which has a number of second ignition orifices defined therein. The encapsulating member defines a plug combustion chamber. The spark plug further includes a center electrode and a ground electrode which are both positioned within the plug combustion chamber. The encapsulating member is positioned relative to the precombustion member such that the plug combustion chamber is in fluid communication with the precombustion chamber via the second ignition orifices.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

Abstract: Disclosed is a method for selectively etching an opening in order to reduce cusping on and thereby widen the opening. The opening in one embodiment comprises a contact opening with a diffusion barrier liner layer deposited thereover that has formed cusps at the mouth of the contact opening. The contact opening is exposed to an etching agent at a low temperature and pressure such that the etching agent adheres to the contact opening. Photons are then directed towards the contact opening at an acute angle to the surface of the contact opening. The acute angle causes the surface of the contact opening to block the photons from contacting the bottom of the contact opening with a high flux density. The photons impart an energy to activate the etching agent, causing substantial etching of an upper portion of the contact opening, while a lower portion does not receive a significant flux density and is not substantially etched.