Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.

Abstract: Silicon substrate having (100) crystal orientation can be wet etched to form (111) sharp tip pyramids. The sharp tip pyramids can be used to fabricate electrodes for flat panel displays, such as a plasma display panel or a field emission display.

Abstract: An anodic etching system for simultaneously etching a multiplicity of substrates comprises: an etching tank for containing therein an etchant solution; a power supply connected between a first electrode and a second electrode, the first electrode and the second electrode being immersible in the etchant solution and positioned at opposite ends of the tank; and a plurality of support plates serially arranged between the first electrode and the second electrode and sealed to walls of the tank, wherein each of the plurality of support plates is configured to support at least one of the multiplicity of substrates, and wherein any consecutive pair of the plurality of support plates defines an isolated volume of the tank for containing a portion of the etchant solution. The plurality of support plates may be susceptors configured for holding the multiplicity of substrates in a chemical vapor deposition tool.

Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

Abstract: This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefitting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride.

Abstract: Multi-layer microscale or mesoscale structures are fabricated with adhered layers (e.g. layers that are bonded together upon deposition of successive layers to previous layers) and are then subjected to a heat treatment operation that enhances the interlayer adhesion significantly. The heat treatment operation is believed to result in diffusion of material across the layer boundaries and associated enhancement in adhesion (i.e. diffusion bonding). Interlayer adhesion and maybe intra-layer cohesion may be enhanced by heat treating in the presence of a reducing atmosphere that may help remove weaker oxides from surfaces or even from internal portions of layers.

Abstract: A seal composition includes a first alkaline earth metal oxide, a second alkaline earth metal oxide which is different from the first alkaline earth metal oxide, aluminum oxide, and silica in an amount such that molar percent of silica in the composition is at least five molar percent greater than two times a combined molar percent of the first alkaline earth metal oxide and the second alkaline earth metal oxide. The composition is substantially free of boron oxide and phosphorus oxide. The seal composition forms a glass ceramic seal which includes silica containing glass cores located in a crystalline matrix comprising barium aluminosilicate, and calcium aluminosilicate crystals located in the glass cores.

Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that (1) partially coats the surface of the structure, (2) completely coats the surface of the structure, and/or (3) completely coats the surface of structural material of each layer from which the structure is formed including interlayer regions. These embodiments incorporate both the core material and the shell material into the structure as each layer is formed along with a sacrificial material that is removed after formation of all layers of the structure. In some embodiments the core material may be a material that would be removed with sacrificial material if it were accessible by an etchant during removal of the sacrificial material.

Abstract: This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefiting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride.

Abstract: A seal composition includes a first alkaline earth metal oxide, a second alkaline earth metal oxide which is different from the first alkaline earth metal oxide, aluminum oxide, and silica in an amount such that molar percent of silica in the composition is at least five molar percent greater than two times a combined molar percent of the first alkaline earth metal oxide and the second alkaline earth metal oxide. The composition is substantially free of boron oxide and phosphorus oxide. The seal composition forms a glass ceramic seal which includes silica containing glass cores located in a crystalline matrix comprising barium aluminosilicate, and calcium aluminosilicate crystals located in the glass cores.

Abstract: A solid oxide fuel cell (SOFC) stack includes a plurality of SOFCs, and a plurality of interconnects, each interconnect containing a conductive perovskite layer on an air side of the interconnect. The stack in internally manifolded for fuel and the conductive perovskite layer on each interconnect is not exposed in the fuel inlet riser. The SOFC electrolyte has a smaller roughness in regions adjacent to the fuel inlet and fuel outlet openings in the electrolyte than under the cathode or anode electrodes.

Abstract: A solar cell may comprise a stack of thin continuous epitaxial single crystal solar cell layers on a single crystal wafer, and a handling layer on the stack, the handling layer having a waffle-shaped structure with an array of either square or circular apertures, wherein the handling layer includes electrical contacts to the stack. The solar cell may comprise a boundary layer between the stack and the handling layer, the boundary layer being attached to both the stack and the handling layer, and the boundary layer being greater than 10 nanometers thick and parallel to the layers in the stack. The waffle-shaped structure may include perpendicular sets of first and second parallel ridges, wherein at least one of the sets is aligned at a small angle to a cleavage plane of the single crystal wafer.

Abstract: A fuel cell stack includes a plurality of fuel cells, a plurality of interconnects, and a plurality of seal members, wherein the plurality of seal members comprises one or more first seal members and one or more additional seal members, where the one or more first seal members form a protective barrier between the reducing environment contained with the fuel cell stack and the remaining seal members.

Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that partially coats the surface of the structure. Other embodiments are directed to electrochemical fabrication methods for producing structures or devices (e.g. microprobes) from a core material and a shell or coating material that completely coats the surface of each layer from which the probe is formed including interlayer regions. Additional embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes) from a core material and a shell or coating material wherein the coating material is located around each layer of the structure without locating the coating material in inter-layer regions.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. A glass/ceramic handling layer is then formed on the PV cell structures. The PV cell structures with handling layers are then exfoliated from the mother wafer. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels. The glass/ceramic handling layers provide structural integrity to the thin epitaxial solar cells during the separation process and subsequent handling.

Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

Abstract: Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn—Pb). Some embodiments provide for reducing tool wear when using difficult-to-machine materials by (1) depositing difficult to machine materials selectively and potentially with little excess plating thickness and/or (2) pre-machining depositions to within a small increment of desired surface level (e.g. using lapping) and then using diamond fly cutting to complete the process, and/or (3) forming structures or portions of structures from thin walled regions of hard-to-machine material as opposed to wide solid regions of structural material.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.