Abstract: The invention relates to a memory circuit comprising a read only memory unit for providing a number of fixed programmed test data; comprising an initialization unit in order, in an initialization mode, to output the fixed programmed test data in a specific sequence to an output terminal.

Abstract: Input circuit and method for setting a termination voltage. One embodiment provides a method for setting a termination voltage of an input circuit of an integrated circuit, the input circuit having an input terminal for receiving a signal, the termination voltage being applied to the input terminal, the received signal being driven with respect to the termination voltage and being evaluated by a comparison with a reference potential, the termination voltage being generated and being set in accordance with a control signal, the control signal being generated in a manner dependent on a comparison of one or more signal levels of the received signal with an assessment potential, the termination voltage being set by means of the control signal in such a way that the reliability of the signal reception is maximized.

Abstract: An integrated semiconductor circuit comprises a substrate with a circuit, a plurality of wiring planes that are isolated from one another and from the substrate by insulator layers, and a signal path for the circuit in the substrate and/or the wiring planes. A first contact terminal, which is formed from a stack of metal areas in a plurality of the wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during a test of the integrated semiconductor circuit. A second contact terminal, which is formed from a metal area or from a stack of metal areas in a plurality of wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during normal operation of the integrated semiconductor circuit.

Abstract: An input circuit for receiving a signal at an input on an integrated circuit, particularly a DRAM circuit, and for assessing the signal with respect to a reference voltage is provided. One embodiment provides a termination circuit for setting a termination voltage, wherein the termination circuit includes a first resistor and a second resistor connected in series between a high voltage potential and a low voltage potential, the termination voltage being tapped between the first and second resistors, a first voltage-dependent resistor element having a first resistance gradient connected in parallel with the first resistor and a second voltage-dependent resistor element having a second resistance gradient connected in parallel with the second resistor, wherein the resistance values of the first and second resistor elements are controlled by a control voltage to set the termination voltage.

Abstract: The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)—, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).

Abstract: An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.

Abstract: A memory device has a memory module, a controller, a data bus for connecting the controller and the memory module, a read clock generator, and a read clock bus for connecting the read clock generator, the memory module, and the Controller. The data bus read data from the memory module or writes data into the memory module. The read clock generator is disposed in the memory module, so that the data bus and the read clock bus are substantially symmetric, and generate a read clock for transferring data from the memory module to the controller. The data bus and the read clock bus are configured with respect to each other such that substantially no time delay between read data on the data bus and the read clock on the read clock bus exists at the controller.

Abstract: A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

Abstract: The present invention provides a wafer handling device having a base plate (G; G′), which has a first and a second supporting surface for a respective wafer (W1, W2) to be laid on; and a fixing device (K1, K2, S; K1′, K2′, S′) for the detachable fixing of the respective wafer (W1, W2) on the first and second supporting surface; the fixing device (K1, K2, S; K1′, K2′, S′) being configured in such a way that it contacts the respective wafer (W1, W2) only in the outer edge region of the side facing away from the supporting surface.

Abstract: Integrated circuit which is integrated in a housing and has a plurality of connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit,

Abstract: An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at least one such arrangement of resistors, wherein the resistors, when viewed in a longitudinal direction of the resistors, are displaced in relation to one another.

Abstract: The invention refers to a circuit device (1) with at least one connection (3b), to which a clock pulse (/CLK, /CLKT) can be applied, whereby the circuit device (1) also comprises a clock pulse detection facility (2) for detecting whether there is a clock pulse (/CLK, /CLKT) present at the connection (3b), or whether there is no clock pulse (/CLK, /CLKT) present at the connection (3b).

Abstract: The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)-, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).

Abstract: A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or falling edge with a different gradient. The output signals of the level converters are combined in a logic combination element. The logic combination element drives a togglable storage element, which provides the level-converted output signal. The duty ratio of the input signal is not changed during the level conversion, independently of production-dictated variations in the component parameters.

Abstract: The invention relates to a voltage supply arrangement for a semiconductor memory with a bus system that is terminated on one side. A terminating voltage supply and a terminating resistor are integrated into a DRAM. The terminating resistor and the terminating voltage supply are extremely stable, so that parasitic events in the terminating resistor are practically precluded.

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

Abstract: The invention relates to a device for generating a refresh signal for a memory cell of a semiconductor memory device, the device comprising:

Abstract: The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

Abstract: A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided with an increased level and therefore cannot be read into the semiconductor memory due to the increased voltage level which functions as a deactivating voltage level.

Abstract: A circuit configuration prevents a transfer of interference signals present on an input line to a processing section. Electrical input signals are evaluated in an analysis circuit which is connected in parallel with the actual reception circuit in a protection device. If an interference signal is present, a transfer circuit is controlled such that a transfer to the processing section is prevented.