Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract: A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link.

Abstract: A compact cassette seal and a corresponding wheel hearing for a passenger car or truck. The cassette seal has a bent sheet-metal ring which is and/or can be non-rotatably connected to a radially inner component and an annular sealing system which is non-rotatably connected to a radially outer component. The sealing system has a bearing ring and a radially peripheral seal with at least one sealing lip. The seal is secured to the bearing ring and the sealing lips resting on the bent sheet-metal ring in a sealing manner. A radially outer ring end section of the sealing system defines a labyrinth seal with a bent sheet-metal section of the bent sheet-metal ring. The bent sheet-metal section radially overlaps the ring end section on the exterior thereby forming an axially aligned or substantially axially aligned labyrinth seal section of the labyrinth seal.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A printing unit of a printing press, such as a web press constructed as a periodical printing press, having at least one printing couple, wherein the printing couple or each printing couple comprises a form cylinder, a transfer cylinder, an inking unit, and preferably a dampening unit. A drive motor is associated with at least one printing couple, and drives the form cylinder or the transfer cylinder of a respective printing couple. In accordance with the invention, a flywheel mass is associated with at least one drive motor which drives the form cylinder or the transfer cylinder of the respective printing couple, where the flywheel mass is connected to the rotor of the respective drive motor in a torsionally rigid manner.

Abstract: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

Abstract: The interchangeable wheel bearing unit has a wheel hub and two tapered roller bearings, each having an outer ring and an inner ring, between which a respective row of tapered rollers is situated, and a securing ring in at least one of the inner rings of the tapered roller bearing. To assemble the wheel bearing unit without special tools, each outer ring of the tapered roller bearings has a cylindrical extension, which runs coaxially with the wheel hub axis towards the outer face of the bearing and into which a respective seal is inserted, and a retaining element, which is supported on the corresponding inner ring and axially fixes the outer ring, is located on the opposite face of the respective tapered roller bearing from the seal.

Abstract: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

Abstract: A method and a device are described for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module by means of a controller, with control bits for adjustment purposes being sent during an adjustment mode by the controller as a burst of data bits at the data clock rate to the RAM module. According to the invention, each control bit which is sent from the controller via the data channel in the burst is represented by a sequence of n?2 data bits, which have a binary value corresponding to the relevant control bit and follow one another at the data clock rate. The binary value of each control bit sent via the data channel is determined in the RAM module by detection of the binary value of the sent burst within the relevant sequence at a time at which the m-th data bit in the sequence appears, where m>1.

Abstract: Seal arrangement for a tire pressure-regulating device for a motor vehicle, comprising a compressed-air supply to a vehicle tire through a hole in the inner ring of a rolling bearing of a wheel bearing, through a seal housing which is connected to a wheel hub in a rotationally fixed manner and through the wheel hub itself, wherein a flat seal is fixed on the inner ring of the rolling bearing, with the radially outer end of the said seal having a sealing lip which is directed towards the seal housing and bears against it.

Abstract: A device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.

Abstract: The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a first nonreactive resistor, and the second of which branch circuits contains an output stage which, in response to the second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a second nonreactive resistor. According to the invention, the driver circuit contains a duty ratio control device for setting the signal propagation time from the input node to the output stage of one branch circuit relative to the signal propagation time from the input node to the output stage of the other branch circuit.

Abstract: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

Abstract: In a semiconductor memory chips, a semiconductor memory system, and a method of masking write data, data, command, and address signal streams are serially transmitted in the form of signal frames in accordance with a predefined protocol. The semiconductor memory system and predefined protocol are adapted to transfer write data mask bits in a close relation to respectively associated write data units within one write data/command stream. An interface section between a reception interface and a memory core of the semiconductor memory chip includes a frame decoder and a intermediate data buffer.

Abstract: A circuit for generating a refresh signal for a memory cell of a semiconductor memory includes a capacitor and a differential current source for providing a charging current to the capacitor. The differential current source includes a temperature-dependent and a temperature-independent current source connected such that the charging current is proportional to a difference between a temperature-dependent current and a temperature-independent current. A comparator a voltage at a capacitor terminal and a reference voltage. The comparator generates a refresh signal when capacitor voltage exceeds the reference voltage.

Abstract: Provided is a semiconductor memory chip that includes a memory core and an interface circuit having decoding, selecting and scheduling circuit means for decoding from a signal frame a respective type of data signals, command signals and address signals, selection of actions which are required in the memory chip according to the respective signal type and scheduling the memory core and sections of the interface circuit respectively for the decoded signal. The interface circuit further comprises a CRC bit decoding and check unit and a protection circuit arranged for protecting the memory core and for enabling/disabling switching through of signal transfer from the interface circuit to the memory core depending on a correct/incorrect signal generated by the CRC bit decoding and check unit according to the result of checking an information within the frame by means of the CRC bits which are inserted in a signal frame in association to the respective information in accordance with a defined transmission protocol.

Abstract: A memory component comprises a memory cell array, signal inputs, input amplifiers connected to respective ones of the signal inputs, for receiving, amplifying and outputting data, address or control signals, a data, address or control signal generator for the memory cell array, a first supply network for supplying power to the input amplifiers and a second supply network for supplying power to the data, address or control signal generator, wherein the first supply network and the second supply network do not have a direct connection.

Abstract: The invention relates to a device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.

Abstract: An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.

Abstract: The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a first nonreactive resistor, and the second of which branch circuits contains an output stage which, in response to the second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a second nonreactive resistor. According to the invention, the driver circuit contains a duty ratio control device for setting the signal propagation time from the input node to the output stage of one branch circuit relative to the signal propagation time from the input node to the output stage of the other branch circuit.