Patents by Inventor Andre Schaefer

Andre Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7321240
    Abstract: The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a first nonreactive resistor, and the second of which branch circuits contains an output stage which, in response to the second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a second nonreactive resistor. According to the invention, the driver circuit contains a duty ratio control device for setting the signal propagation time from the input node to the output stage of one branch circuit relative to the signal propagation time from the input node to the output stage of the other branch circuit.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: January 22, 2008
    Assignee: Infineon Technologies AG
    Inventor: Andre Schaefer
  • Publication number: 20070091711
    Abstract: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Paul Wallner, Andre Schaefer, Thomas Hein, Peter Gregorius
  • Publication number: 20070061494
    Abstract: In a semiconductor memory chips, a semiconductor memory system, and a method of masking write data, data, command, and address signal streams are serially transmitted in the form of signal frames in accordance with a predefined protocol. The semiconductor memory system and predefined protocol are adapted to transfer write data mask bits in a close relation to respectively associated write data units within one write data/command stream. An interface section between a reception interface and a memory core of the semiconductor memory chip includes a frame decoder and a intermediate data buffer.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 15, 2007
    Inventors: Paul Wallner, Andre Schaefer, Thomas Hein
  • Patent number: 7180805
    Abstract: A circuit for generating a refresh signal for a memory cell of a semiconductor memory includes a capacitor and a differential current source for providing a charging current to the capacitor. The differential current source includes a temperature-dependent and a temperature-independent current source connected such that the charging current is proportional to a difference between a temperature-dependent current and a temperature-independent current. A comparator a voltage at a capacitor terminal and a reference voltage. The comparator generates a refresh signal when capacitor voltage exceeds the reference voltage.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: February 20, 2007
    Assignee: Infineon Technologies AG
    Inventors: Joachim Schnabel, Andre Schaefer
  • Publication number: 20070006057
    Abstract: Provided is a semiconductor memory chip that includes a memory core and an interface circuit having decoding, selecting and scheduling circuit means for decoding from a signal frame a respective type of data signals, command signals and address signals, selection of actions which are required in the memory chip according to the respective signal type and scheduling the memory core and sections of the interface circuit respectively for the decoded signal. The interface circuit further comprises a CRC bit decoding and check unit and a protection circuit arranged for protecting the memory core and for enabling/disabling switching through of signal transfer from the interface circuit to the memory core depending on a correct/incorrect signal generated by the CRC bit decoding and check unit according to the result of checking an information within the frame by means of the CRC bits which are inserted in a signal frame in association to the respective information in accordance with a defined transmission protocol.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Paul Wallner, Andre Schaefer, Thomas Hein, Peter Gregorius
  • Publication number: 20060233005
    Abstract: The invention relates to a device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.
    Type: Application
    Filed: March 21, 2006
    Publication date: October 19, 2006
    Inventors: Andre Schaefer, Thomas Hein, Christian Weis
  • Publication number: 20060170456
    Abstract: The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a first nonreactive resistor, and the second of which branch circuits contains an output stage which, in response to the second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a second nonreactive resistor. According to the invention, the driver circuit contains a duty ratio control device for setting the signal propagation time from the input node to the output stage of one branch circuit relative to the signal propagation time from the input node to the output stage of the other branch circuit.
    Type: Application
    Filed: December 22, 2005
    Publication date: August 3, 2006
    Inventor: Andre Schaefer
  • Publication number: 20060152957
    Abstract: An inventive circuit arrangement for setting selected operating parameters in a RAM module contains, for each element in a set of M different operating parameters, a respective value register which is individually assigned, can be set using an individual control signal and is intended to store an item of value information that has been input for the relevant parameter. A first group of external terminals is dedicated to inputting destination information which indicates the respective parameter to be set, and a second group of external terminals is dedicated to inputting value information for the parameters. Provision is also made of a selection device which can be controlled using the destination information which has been input at the first group of terminals in order to transmit the value information which has been input at the second group of terminals only to that value register which is assigned to the indicated parameter.
    Type: Application
    Filed: October 26, 2005
    Publication date: July 13, 2006
    Inventor: Andre Schaefer
  • Patent number: 7068079
    Abstract: The invention refers to a circuit device (1) with at least one connection (3b), to which a clock pulse (/CLK, /CLKT) can be applied, whereby the circuit device (1) also comprises a clock pulse detection facility (2) for detecting whether there is a clock pulse (/CLK, /CLKT) present at the connection (3b), or whether there is no clock pulse (/CLK, /CLKT) present at the connection (3b).
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: June 27, 2006
    Assignee: Infineon Technologies AG
    Inventors: Andre Schaefer, Johann Pfeiffer, Kasimierz Szczypinski, Joachim Schnabel
  • Patent number: 7049930
    Abstract: An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at least one such arrangement of resistors, wherein the resistors, when viewed in a longitudinal direction of the resistors, are displaced in relation to one another.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: May 23, 2006
    Assignee: Infineon Technologies AG
    Inventors: Joachim Schnabel, Andre Schaefer, Xaver Obergrussberger, Sebastian Mosler
  • Publication number: 20060085705
    Abstract: The invention relates to a memory circuit comprising a read only memory unit for providing a number of fixed programmed test data; comprising an initialization unit in order, in an initialization mode, to output the fixed programmed test data in a specific sequence to an output terminal.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 20, 2006
    Inventor: Andre Schaefer
  • Publication number: 20060049511
    Abstract: An integrated semiconductor circuit comprises a substrate with a circuit, a plurality of wiring planes that are isolated from one another and from the substrate by insulator layers, and a signal path for the circuit in the substrate and/or the wiring planes. A first contact terminal, which is formed from a stack of metal areas in a plurality of the wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during a test of the integrated semiconductor circuit. A second contact terminal, which is formed from a metal area or from a stack of metal areas in a plurality of wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during normal operation of the integrated semiconductor circuit.
    Type: Application
    Filed: August 29, 2005
    Publication date: March 9, 2006
    Inventor: Andre Schaefer
  • Patent number: 6917562
    Abstract: The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)—, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: July 12, 2005
    Assignee: Infineon Technologies AG
    Inventors: Andre Schaefer, Johann Pfeiffer, Kazimierz Szczypinski
  • Patent number: 6911732
    Abstract: An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: June 28, 2005
    Assignee: Infineon Technologies AG
    Inventors: Simon Muff, Martin Gall, Andre Schaefer, Georg Braun
  • Patent number: 6783596
    Abstract: The present invention provides a wafer handling device having a base plate (G; G′), which has a first and a second supporting surface for a respective wafer (W1, W2) to be laid on; and a fixing device (K1, K2, S; K1′, K2′, S′) for the detachable fixing of the respective wafer (W1, W2) on the first and second supporting surface; the fixing device (K1, K2, S; K1′, K2′, S′) being configured in such a way that it contacts the respective wafer (W1, W2) only in the outer edge region of the side facing away from the supporting surface.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: August 31, 2004
    Assignee: Infineon Technologies AG
    Inventors: Andre Schaefer, Andrea Zuckerstaetter
  • Publication number: 20040145036
    Abstract: Integrated circuit which is integrated in a housing and has a plurality of connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit,
    Type: Application
    Filed: April 30, 2002
    Publication date: July 29, 2004
    Inventors: Simon Muff, Martin Gall, Andre Schaefer, Georg Braun
  • Publication number: 20040130433
    Abstract: An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at least one such arrangement of resistors, wherein the resistors, when viewed in a longitudinal direction of the resistors, are displaced in relation to one another.
    Type: Application
    Filed: September 16, 2003
    Publication date: July 8, 2004
    Inventors: Joachim Schnabel, Andre Schaefer, Xaver Obergrussberger, Sebastian Mosler
  • Publication number: 20040124887
    Abstract: The invention refers to a circuit device (1) with at least one connection (3b), to which a clock pulse (/CLK, /CLKT) can be applied, whereby the circuit device (1) also comprises a clock pulse detection facility (2) for detecting whether there is a clock pulse (/CLK, /CLKT) present at the connection (3b), or whether there is no clock pulse (/CLK, /CLKT) present at the connection (3b).
    Type: Application
    Filed: September 23, 2003
    Publication date: July 1, 2004
    Inventors: Andre Schaefer, Johann Pfeiffer, Kasimierz Szczypinski, Joachim Schnabel
  • Publication number: 20040124886
    Abstract: The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)-, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).
    Type: Application
    Filed: September 10, 2003
    Publication date: July 1, 2004
    Applicant: Infineon Technologies AG
    Inventors: Andre Schaefer, Johann Pfeiffer, Kazimierz Szczypinski
  • Patent number: 6690612
    Abstract: The invention relates to a voltage supply arrangement for a semiconductor memory with a bus system that is terminated on one side. A terminating voltage supply and a terminating resistor are integrated into a DRAM. The terminating resistor and the terminating voltage supply are extremely stable, so that parasitic events in the terminating resistor are practically precluded.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: February 10, 2004
    Assignee: Infineon Technologies AG
    Inventors: Martin Gall, Andre Schaefer