Abstract: Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet.

Abstract: Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device (30) having two full-duplex gigabit ports. According to one aspect of the invention, the switches (20, 30) are connected in a ring using their respective gigabit ports, with each of the switches (20, 30) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches. (20) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches (20, 30), or until the packet returns to the original switch (20) which, upon detecting its own Ring ID value, filters or discards the packet.

Abstract: An improved communications system with a circuit having a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution is provided. More particularly, the system has a first memory, a plurality of protocol handlers, a bus connected to said protocol handlers, a second memory connected to said bus, and a memory controller connected to said bus and said second memory for selectively comparing addresses, transferring data between said protocol handlers and said second memory, and transferring data between said second memory and said first memory. A first embodiment is a local area network controller having a first circuit having a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution, and an address lookup circuit interconnected to said first circuit.

Abstract: The present invention includes an improved switching device (400) which operates in a shared media environment. The switching device (400) in accordance with the present invention includes a tag header processing means (402) operable to insert a tag header into frames that enter the switching device (400) without a tag header and CRC processing means (404) operable to calculate a CRC for the frame excluding the tag header for use while the frame is being processed within the switching device (400). The tag header processing means (402) is further operable, when the internal switch processing of the frame is completed and the frame is ready to be transmitted, to determine whether or not the frame should be transmitted without a tag header and removing the tag header if it is not.

Abstract: An improved network extender module 6 connects multiple data sources (1 and 2) to a network 3. This invention facilitates the addition of a Voice over Internet Protocol (VoIP) telephone 1 to be added to a system without any significant degradation in the performance of data transmission between a computer workstation 2 and a network 3.

Abstract: A network switch system (10) is disclosed, in which a plurality of switch fabric devices (20) are interconnected according to a ring arrangement, each of the switch fabric devices (20) including therein switch interfaces (22) coupled to corresponding network switches (14, 16). Each switch fabric device includes a plurality of ring paths (24), each of which is associated with a receive ring interface (26R) and a transmit ring interface (26X). Each ring path (24) includes a circular buffer (44) having a plurality of entries, each of which is associated with valid logic (50). The valid logic (50) for each entry presents valid signals on valid lines (WV, RV) to the receive and transmit domains of the ring path (24), and receives signals on write and read word request lines (WRW, RDW) therefrom.

Abstract: A data aliginmentation apparatus and method in a LAN adapter. The arrangement includes a data aligner mechanism and a transfer control mechanism that transfer data between this RAM and a PCI bus. A transfer control mechanism pre-calculates the control parameters for the aligner/data-pipe, creates the necessary byte enables for data transfers, and determines the number of transfers needed. This allows the data aligner to create a stream of data words for any arbitrary byte transfer with full PCI data streaming (one 32 bit word every PCI clock cycle).The Data Aligner provides a shifter and data-pipe that is used to convert the RAMs 64 bit words into PCIs 32 bit words. It is bidirectional and is used to convert 64 bit data from the RAM into 32 bit PCI word(s) and vice versa.

Abstract: This invention relates to an improved LAN adapter. The LAN adapter includes a time division multiplex (TDM) ported RAM. The RAM is used to provide both network data FIFOs and control data storage in a single memory element. The network and peripheral components are able to access the same memory, but at different times in the cycle, thereby minimizing the component count and optimizing the operation of the adapter.

Abstract: A local area network ("LAN") controller operable in an IEEE 802.3u network and an IEEE 802.12 network. A common physical connector is used for both standards, attached to an attachment medium such as a card. An 802.3u circuit is attached to the card, implementing the following 802.3u functions: A media access controller ("MAC") layer, and a physical media independent ("PMI") layer that provides the IEEE 802.3u media independent interface ("MII"). An 802.12 circuit is also attached to the card, implementing the following IEEE 802.12 functions: An LLC layer, an MAC layer, and a PMI layer, providing an MII to a device implementing an 802.12 physical media dependent ("PMD") layer. A circuit coupled to the 802.12 circuit multiplexes, according to a predetermined strategy, 802.12 PMI to PMD signals over the physical connector and, alternatively, communicates 802.3u MII signals between the 802.3u circuit and the physical connector.

Abstract: A data alignmentation apparatus and method in a LAN adapter. The arrangement includes a data aligner mechanism and a transfer control mechanism that transfer data between this RAM and a PCI bus. A transfer control mechanism pre-calculates the control parameters for the aligner/data-pipe, creates the necessary byte enables for data transfers, and determines the member of transfers needed. This allows the data aligner to create a stream of data words for any arbitrary byte transfer with full PCI data streaming (one 32 bit word every PCI clock cycle).The Data Aligner provides a shifter and data-pipe that is used to convert the RAMs 64 bit words into PCIs 32 bit words. It is bidirectional and is used to convert 64 bit data from the RAM into 32 bit PCI word(s) and vice versa.

Abstract: A communications network adapter of the type coupling a computer, in which the computer includes a microprocessor, main memory and a system bus, that controls host interrupts in a manner to improve system performance. The adapter includes a buffer memory for storing data to be transferred between the bus an the network, and a transfer controller that controls the transfer of data between the main memory and the buffer memory and between the network and the buffer memory. The adapter also includes an interrupt controller that monitors predetermined events relating to data transfer between the computer and the network, and that causes the sending of interrupt signals to the microprocessor. Interrupt signals cause the microprocessor to initiate processing associated with the transfer of data between the computer and the network.

Abstract: A data communications system memory interface circuit (32) is provided which operates within an adapter circuit (10). Adapter circuit (10) comprises a communications processor (28), a system interface (30) and a protocol handler (20) coupled together by an adapter bus (26). Communications processor (28) accesses an external memory (38) through a memory interface (32). Memory interface (32) comprises a map register circuit (36) which comprises a number of map registers (44 through 56). The map registers (44 through 56) each are operable to store a portion of a twenty bit address which may be selected by a multiplexer (42) responsive to control signals generated by a control logic circuit (40). The address portion stored in the map registers (44 through 56) are added to a remaining portion of an address to form a complete twenty bit remapped address.

Abstract: Circuitry for switching between a first and second clock signal is provided having a first local clock circuit 202, a first synchronizing circuit 200 connected to said first clock circuit 202, a first delay circuit 206a-d connected to said first synchronizing circuit 200 and said first clock circuit 202, a second delay circuit 206e, 210, connected to said first delay circuit 206a-d and said first clock circuit 202, a first logic circuit 220 connected to said first 206a-d and second 206e, 210 delay circuits and said first synchronizing circuit 200, a second local clock circuit 102, a second synchronizing circuit 100 connected to said second clock circuit 102, a third delay circuit 106, 108, 110, connected to said second synchronizing circuit 100 and said second clock circuit 102, a second logic circuit 104 connected to said second clock circuit 102 and a portion of said third delay circuit 106, 108, 110, a third logic circuit 120 connected to said third delay circuit 106, 108, 110, and said second clock circui

Abstract: Circuitry 10 is provided that contains two (or more) PLA matrix structures 12, 14 which share at least some outputs and are interconnected with a common output structure 18, individual input 30 and output 42, 62 structures, and an appropriate controller 28 for selecting which PLA matrix structure 12, 14 is to be employed. A common input structure 16 may be interconnected with the PLA matrix structures 12, 14 employed. The controller 28 may also be employed to power-down the PLA matrix structures not employed. The controller 28 may be static and select one matrix structure until reset, or dynamic and change as a function of some control signal.

Abstract: A communications processor system 10b that permits communications task code to be safely downloaded from a host system. Direct access to local memory 15b of the communications processor system 10b is permitted only during a downloading process while system 10b in a reset state. This downloading process is implemented with a special control register. In user mode, the system 10b controls access to local memory 15b by downloaded task code. Specifically, access is prohibited with respect to privileged memory areas, and is limited to a relatively small predetermined range of addresses with respect to other memory areas. This memory protection process is implemented with a special status register and a number of mapping registers.

Abstract: An adapter circuit for a local area network is disclosed, which contains logic external to the protocol handler for address comparison. The adapter uses random-access memory to store the data fields arriving after the address fields in the serial input data stream during such time as the adapter is comparing the address fields to its own address. The portion of memory used for the data storage is overwritten (recovered) by the next frame of data if the particular adapter was not addressed by the prior frame; the portion of memory used for the data storage is not overwritten if the data was addressed to the adapter. The protocol handler circuit performs an address comprising internally thereto, for intra-ring communication, and controls the recovery of the memory dependent upon the results of the comparison. The external logic performs an address comparison, primarily in inter-ring communication.

Abstract: An interface device is provided for coupling a host device having a network interface to a computer network having a predetermined communications medium and a predetermined communications physical layer. The interface device comprises a plug member having a first connector affixed to it for coupling to the network interface of the host device. The interface device further includes front end circuitry disposed within the plug member, the front end circuitry being selectable to couple to the predetermined communications medium and to interact with the predetermined physical layer.

Abstract: The present embodiment includes a local area network adaptive circuit for coupling a host device to a network front end circuit which communicates information to/from a network. The adaptive circuit comprises an internal bus, a first bus operable to communicate with a bus of the host device and with the internal bus, and a second bus operable to communicate with a bus of the front end circuit and with the internal bus. The adaptive circuit further includes a protocol handler. The protocol handler is operable to communicate with the first, second and internal buses for communicating with either a token ring or an ethernet protocol in a token ring or protocol mode, respectively.

Abstract: A signal interface is provided for coupling a network front end circuit to a network adapter circuit, wherein the network front end circuit communicates with a network. The signal interface comprises a plurality of input signal lines, each operable to conduct an input signal from the network front end circuit to the network adapter circuit. The signal interface further comprises a plurality of output signal lines, each operable to conduct an output signal from the network adapter circuit to the network front end circuit. Selected ones of the input and output signal lines are functional to support both a first and second network protocol on the same line. Further, only input signals are input on the selected input lines and only output signals are output on the selected output lines.

Abstract: The present invention includes a data transfer system (28) which includes a first bus (32) and a second bus (34) wherein both buses are bidirectionally connected to a first memory (30). Similarly, a third bus (42) and a fourth bus (44) are bidirectionally connected to a second memory (40). A plurality of data cells (50a through 50h) are provided for intermediate storage when units of information are transferred between first and second memories (30 and 40). A first pointer (37) is under control of first pointer circuit (36) and first control circuit (38) such that buses (32 and 34) may have access to selected ones of the plurality of data cells (50a through 50h). Similarly, a second pointer (47) is under control of second pointer circuit (46) and second control circuit (48) such that third and fourth buses (42 and 44) may have access to the plurality of data cells (50a through 50h).