Abstract: An elastic buffer for absorbing frequency jitter or drift of an incoming data signal which includes a serial stack of data registers. These data registers are used for storing data bits from an incoming data stream one at a time with each bit adjacent a next earlier bit at a frequency equal to the frequency of the incoming data and also for releasing stored bits onto an output data line. The stored bits are released one at a time at a predetermined fixed rate equal to the average frequency of incoming data from a number of registers away from the register into which data is being written which depends on the frequency difference between incoming data and the fixed rate aforesaid.

Abstract: In a content addressable memory, a plurality of equal-sized groups of data bits are accessed simultaneously from a memory and compared with a sequence of groups from an input key code, each group consisting of the same number of consecutive data bits. Each comparison of groups of data bits produces a match indication, and a comparison of groups of data bits is inhibited unless the comparison of the preceding group of memory data bits with the preceding group of key code data bits produced a positive match indication. The match indications are stored in a shift register, which is shifted one step after each comparison to permit or inhibit the next comparison. The memory may be a dynamic semiconductor RAM accessed a row at a time. The data bits from a single row access may be compared in time with the groups of a plurality of groups of data bits, say 4, constituting the entire input key code.

Abstract: A method of comparing two binary quantities, which includes comparing corresponding bits of each of the binary quantities and generating comparison signals to indicate equality and inequality of corresponding bits of the quantities. The comparison signals are transferred to a transfer line with the signals being arranged in order on the transfer line from the signal corresponding to the most significant bits to that corresponding to the least significant bits. A selected number of the comparison signals are coupled in order of priority from that corresponding to the most significant bits to that corresponding to the least significant bits, to an output EQUALS line in response to a plurality of decode signals.

Abstract: An adapter circuit for a local area network is disclosed, which contains logic external to the protocol handler for address comparison. The adapter uses random-access memory to store the data fields arriving after the address fields in the serial input data stream during such time as the adapter is comparing the address fields to its own address. The portion of memory used for the data storage is overwritten (recovered) by the next frame of data if the particular adapter was not addressed by the prior frame; the portion of memory used for the data storage is not overwritten if the data was addressed to the adaptor. The protocol handler circuit performs an address comparison internally thereto, for intra-ring communication, and controls the recovery of the memory dependent upon the results of the comparison. The external logic performs an address comparison, primarily in inter-ring communication.

Abstract: A fairness protocol circuit for a token ring local area network adaptor having a data-in line for serially carrying tokens/frames and a shift register delay of at least 18 bauds with an input coupled to the data-in line. A TTT stack is coupled to the shift register delay for serially storing values of old token indicators. An III stack is provided for serially storing values of new token priority indicators. TTT means is coupled to the TTT stack for temporarily storing a last old token placed on the TTT stack and serially outputting its bits. The stacks shift up or down bit by bit in response to UNSTACK or STACK control signals and are cleared in response to a clear signal.

Abstract: A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbitration latch has a bistable device the state of which determines which processor has access to the memory. The outputs of the bistable device have threshold devices which have threshold levels higher than the signal outputs of the bistable device when it is in a metastable state, so that there is no possibility that both processors could have access to the memory at the same time. Data and address registers for the two processors are selectively connectible to the random access memory through multiplexers controlled by the arbitration latch.

Abstract: A token ring access control protocol circuit which includes an M/T converter for converting incoming serial data in differential Manchester encoded form into transitional encoded form. Next the data is fed into a shift register and held temporarily while it is compared with preset sequences to determine if it is a starting delimiter or an ending delimiter. If a starting delimiter pulse is generated and used to synchronize subsequent circuitry if required. Data from the shift register is continuously sampled with at least a 2 baud delay by a data sample latch circuit which provides and output line for data values and another output line for code violation signals. The data values and code violation values go to a data receiving circuit which processes the data, and loads it onto a local data bus for transmission to other parts of a token ring control system.