Abstract: A hypervisor on a destination host receives a request to migrate a virtual machine (VM) from a source host to the destination host and determines a total amount of memory associated with the VM on the source host. The hypervisor on the destination host allocates one or more memory pages in a page table on the destination host to satisfy the total amount of memory associated with the VM on the source host, where the one or more memory pages are to be associated with the VM on the destination host. Responsive to determining that the one or more memory pages have been allocated on the destination host, the hypervisor on the destination host initiates migration of the VM from the source host to the destination host.

Abstract: A driver associated with a host peripheral component interconnect (PCI) device may be initiated, the host PCI device to be accessed by an application executed by a guest operating system (OS) of a guest using user space memory of the guest. A host page table switching instruction may be executed using the driver to cause a switch from a first host page table structure to a second host page table structure. The host PCI device may be accessed using the driver via a PCI alias address that is mapped to a host PCI address in the second host page table structure. Application code associated with the application may be prevented from accessing a host memory address in the second host page table structure.

Abstract: A system includes a memory, at least one physical processor in communication with the memory, and a plurality of hardware threads executing on the at least one physical processor. A first thread of the plurality of hardware threads is configured to execute a plurality of instructions that includes a restartable sequence. Responsive to a different second thread in communication with the first thread being pre-empted while the first thread is executing the restartable sequence, the first thread is configured to restart the restartable sequence prior to reaching a memory barrier.

Abstract: Systems and methods for thread execution transition are disclosed. An example system includes a memory and a processor with first and second registers. An application and a supervisor are configured to execute on the processor, which suspends execution of a first thread executing the supervisor. One execution state of the first thread is stored in the first register. The application stores a request in a first shared memory location. The application executes on a second thread and another execution state of the second thread is stored in the second register. The processor suspends execution of the second thread and resumes execution of the first thread. The supervisor retrieves data for the request from the first shared memory location, and processes the data, including storing a result to a second shared memory location. The processor suspends execution of the first thread and resumes execution of the second thread.

Abstract: A system includes a memory, a processor in communication with the memory, an application, and a supervisor. The supervisor is configured to allocate an identifier corresponding to a virtual memory area and expose a data structure that is readable by the application. Responsive to a fault trigger associated with an address, the supervisor is configured to record fault information in the data structure. The application is configured to predict at least a portion of subsequent fault information based on fault information recorded in the data structure.

Abstract: A method for a virtual machine executed by a hypervisor includes identifying, for the virtual machine, mappings between a range of guest virtual addresses (GVAs) and a range of guest physical addresses (GPAs) that remain the same in an initial guest page table for a threshold period of time, creating an intermediate guest page table including one or more page table entries that map the range of the GVAs to a range of guest intermediate addresses (GIAs), and causing the GVA to be translated to a GIA using the intermediate guest page table in view of the one or more page table entries, where the translation is triggered responsive to a guest application of the virtual machine attempting to access a GVA in the range of the GVAs.

Abstract: Aspects of the disclosure provide for implementing host address space identifiers for non-uniform memory access (NUMA) locality in virtual machines. A method of the disclosure includes determining, by a virtual machine (VM) executed by a processing device and managed by a hypervisor, that a memory page of the guest is to be moved from a first virtual non-uniform memory access (NUMA) node of the VM to a second virtual NUMA node of the VM. The method further includes updating, by the VM in a guest page table, upper bits of a guest physical address (GPA) of the memory page to include a host address space identifier (HASID) of the second virtual NUMA node, and causing an execution control to be transferred from the VM to the hypervisor due to a page fault resulting from attempting to access the updated GPA.

Abstract: A method of migrating memory includes protecting, by a hypervisor, a first memory page from write operations, the first memory page being used for direct memory access (DMA) by a device and stored at a guest memory address that maps to a first host-physical address. A second memory page is stored at the first host-physical address, and the device is allowed DMA in an input/output memory management unit (IOMMU). The method also includes allocating a third memory page at a second host-physical address and copying data stored at the second memory page to the third memory page. The method further includes updating a mapping including the guest memory address to reference the second host-physical address and detecting that the first memory page is protected from write operations by the device. The method further includes pinning the second memory page to main memory of the host machine and storing the mapping.

Abstract: Aspects of the disclosure provide for host address space identifiers for non-uniform memory access (NUMA) locality in virtual machines. A method of the disclosure includes receiving, by a hypervisor executed by a processing device of a host machine, execution control from a guest managed by the hypervisor, wherein a page fault corresponding to a guest physical address (GPA) triggered an exit to the hypervisor from the guest, identifying a host address space identifier (HASID) from the GPA, determining, in view of the HASID, whether to migrate a memory page associated with the GPA to a destination host non-uniform memory access (NUMA) node corresponding to the HASID, and creating a new page table entry for the GPA in a host page table of the hypervisor.

Abstract: A driver associated with a host peripheral component interconnect (PCI) device may be initiated, the host PCI device to be accessed by an application executed by a guest operating system (OS) of a guest using user space memory of the guest. A host page table switching instruction may be executed using the driver to cause a switch from a first host page table structure to a second host page table structure. The host PCI device may be accessed using the driver via a PCI alias address that is mapped to a host PCI address in the second host page table structure. Application code associated with the application may be prevented from accessing a host memory address in the second host page table structure.

Abstract: A method for a virtual machine executed by a hypervisor including receiving a first request to execute a first guest application in the virtual machine, and locating, in view of a first memory context tag associated with the first guest application, an intermediate guest page table including a first mapping of a first range of guest virtual addresses (GVAs) to a first range of guest intermediate addresses (GIAs). The first range of GIAs is allocated for the first guest application in a guest physical address space separate from other addresses in the guest physical address space mapped to random access memory (RAM) for the virtual machine. The method also includes executing the first guest application using the first mapping of the first range of GVAs to the first range of GIAs allocated for the first guest application.

Abstract: A system and method of de-duplication includes receiving a first page, scanning a first structure, identifying a first match, determining a quantity of mappings to the first match is less than a threshold, and adding a first mapping to the first match. The method includes receiving a second page, scanning the first structure, identifying the first match, determining the quantity of mappings to the first match meets the threshold, and storing the second page in a second structure. The method includes receiving a third page, scanning the first structure, identifying the first match, determining the quantity of mappings to the first match meets the threshold, scanning the second structure, identifying the second page as the match, and creating a third structure that replaces the first match and includes an identifier node, the first match, and a second match with the second and third mapping identifying the second and third pages.

Abstract: Systems and methods that enable user space processing threads to handle hardware events (e.g., page faults) for another processing thread in a security-enhanced manner. An example method may comprise: associating, by a processing device executing a kernel, a first processing thread with a storage unit of a second processing thread; detecting, by a processing device, a hardware event corresponding to an address of the storage unit; determining a storage object comprising data of the storage unit; translating the address of the storage unit to an offset of the storage object; and transmitting, by the kernel, a notification of the hardware event to the first processing thread, wherein the notification comprises the offset.

Abstract: A method for a virtual machine executed by a hypervisor including receiving a first request to execute a first guest application in the virtual machine, and locating, in view of a first memory context tag associated with the first guest application, an intermediate guest page table including a first mapping of a first range of guest virtual addresses (GVAs) to a first range of guest intermediate addresses (GIAs). The first range of GIAs is allocated for the first guest application in a guest physical address space separate from other addresses in the guest physical address space mapped to random access memory (RAM) for the virtual machine. The method also includes executing the first guest application using the first mapping of the first range of GVAs to the first range of GIAs allocated for the first guest application.

Abstract: A method for a virtual machine executed by a hypervisor includes identifying, for the virtual machine, mappings between a range of guest virtual addresses (GVAs) and a range of guest physical addresses (GPAs) that remain the same in an initial guest page table for a threshold period of time, creating an intermediate guest page table including one or more page table entries that map the range of the GVAs to a range of guest intermediate addresses (GIAs), and causing the GVA to be translated to a GIA using the intermediate guest page table in view of the one or more page table entries, where the translation is triggered responsive to a guest application of the virtual machine attempting to access a GVA in the range of the GVAs.

Abstract: Aspects of the disclosure provide for host address space identifiers for non-uniform memory access (NUMA) locality in virtual machines. A method of the disclosure includes receiving, by a hypervisor executed by a processing device of a host machine, execution control from a guest managed by the hypervisor, wherein a page fault corresponding to a guest physical address (GPA) triggered an exit to the hypervisor from the guest, identifying a host address space identifier (HASID) from the GPA, determining, in view of the HASID, whether to migrate a memory page associated with the GPA to a destination host non-uniform memory access (NUMA) node corresponding to the HASID, and creating a new page table entry for the GPA in a host page table of the hypervisor.

Abstract: Systems and methods that enable user space processing threads to handle hardware events (e.g., page faults) for another processing thread in a security-enhanced manner. An example method may comprise: associating, by a processing device executing a kernel, a first processing thread with a storage unit of a second processing thread; detecting, by a processing device, a hardware event corresponding to an address of the storage unit; determining a storage object comprising data of the storage unit; translating the address of the storage unit to an offset of the storage object; and transmitting, by the kernel, a notification of the hardware event to the first processing thread, wherein the notification comprises the offset.

Abstract: A system and method for an active Q-switched fiber laser cavity may include a pump source for emitting a laser beam at a wavelength along an optical path including an active optical medium. A modulation device may be configured to introduce tunable losses into the optical path. The tunable losses may be achieved through modulation of the transmissivity of an optical element within the optical path, the modulation of said optical element being performed over (i) a first period of time in which a cavity Q curve increases from a first percentage value to a second percentage value of a maximum Q value and (ii) a second period of time in which the cavity Q curve increases from a third percentage value to a fourth percentage value of the maximum Q value. The cavity Q curve may non-linearly and smoothly transition between (i) the first and second percentage values and (ii) the third and fourth percentage values.

Abstract: A guest OS detects a DMA write request for a device assigned to the guest OS to perform a DMA write to a shared page of memory that has a write protection attribute to cause a protection page fault upon an attempt to write to the shared page of memory. The guest OS reads a portion of the shared page of memory from a location of that page, determines the value of the portion, and executes an atomic instruction that writes the value back to the location of the shared page of memory to trigger the page protection fault. Upon executing the atomic instruction, the guest OS sends the DMA write request to the device to cause the device to write to a writeable copy of the shared page of memory.

Abstract: Systems and methods for providing dynamic processor topology information to a virtual machine hosted by a multi-processor computer system supporting non-uniform memory access (NUMA). An example method may comprise assigning a unique identifier to a virtual processor, determining that the virtual processor has been moved from a first physical processor to a second physical processor, determining a memory access latency value for the second physical processor, and updating an element of a data structure storing memory access latency information with the memory access latency value of the second physical processor, the element identified by the unique identifier of the virtual processor.