Abstract: An assembly as discussed herein includes: a first semiconductor chip substrate including an active region and an inactive region, the active region of the first semiconductor chip substrate fabricated to include first circuitry, the first circuitry being active circuitry, the inactive region of the first semiconductor chip substrate being void of active circuitry; and second circuitry coupled to the first semiconductor chip substrate, the second circuitry affixed to the inactive region of the first semiconductor chip substrate, the inactive region operative to receive and convey heat generated by the second circuitry.

Abstract: A power semiconductor package includes: a metal plate having opposing first and second sides; a lateral wall extending along a rim of the first side of the metal plate and surrounding an inner portion of the first side; at least one die carrier arranged over the inner portion of the first side of the metal plate; a power semiconductor die arranged over and electrically coupled to the die carrier, the die carrier electrically isolating the power semiconductor die from the metal plate; and a printed circuit board (PCB) arranged over the lateral wall and covering the inner portion of the first side of the metal plate such that the die carrier and the power semiconductor die are arranged within an interior volume of the power semiconductor package encapsulated by the inner portion of the first side of the metal plate, the lateral wall and the PCB.

Abstract: A semiconductor package includes: a molded body having opposite first and second sides; at least one semiconductor die encapsulated by the molded body; and a die carrier having opposite first and second sides. The semiconductor die is arranged over the first side of the die carrier. The second side of the die carrier is at least partially exposed from the second side of the molded body, forming at least one exposed portion of the die carrier. The first side of the molded body includes a first portion protruding from a second portion in a vertical direction perpendicular to the first side, forming a planar surface. The second portion extends completely along at least one edge of the first side. A center point of the first portion is in vertical alignment with a center point of the exposed portion.

Abstract: A molded electronic component includes a mold compound, a die assembly, a plurality of metallic loops, and a metallic body. The die assembly includes a semiconductor die attached to a substrate. The die assembly is at least partly embedded in the mold compound. The plurality of metallic loops is embedded in the mold compound and attached to the die assembly. The metallic body is partly embedded in the mold compound and has a first surface that is exposed from the mold compound. The metallic body is attached to each of the plurality of metallic loops at a second surface of the metallic body opposite the first surface.

Abstract: A power semiconductor assembly includes: a power semiconductor die having opposing first and second sides; a metal substrate having opposing first and second sides, the first side having a recess in which the power semiconductor die is arranged such that the second side of the power semiconductor die faces a bottom side of the recess; a printed circuit board (PCB) having opposing first and second sides, the power semiconductor die and metal substrate being embedded within the PCB; a power electronic substrate arranged below the second side of the PCB and coupled via a solder joint to a metal layer on the second side of the PCB; and a dielectric material layer arranged between the second side of the PCB and the power electronic substrate and arranged laterally next to the solder joint, the dielectric material layer coupling the PCB to the power electronic substrate via a fused joint.

Abstract: A device for forming a housing for a power semiconductor module arrangement includes a mold. The mold includes a first cavity including a plurality of first openings and a second opening, the second opening being coupled to a runner system, wherein the runner system is configured to inject a mold material into the first cavity through the second opening. The device further includes a plurality of sleeves or hollow bushings, wherein a first end of each of the plurality of sleeves or hollow bushings is arranged in one of the first openings, and wherein a second end of each of the plurality of sleeves or hollow bushings extends to the outside of the mold, a heating element configured to heat the mold, and a cooling element configured to cool the plurality of sleeves or hollow bushings.

Abstract: A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.

Abstract: A power module includes: a lead frame having a base region and leads; a plurality of substrates each having a first metallized side attached to the base region of the lead frame, a second metallized side opposite the first metallized side, and an insulating body that electrically isolates the first and second metallized sides from one another; at least one semiconductor die attached to the second metallized side of each substrate; and a mold compound encapsulating the semiconductor dies and part of the lead frame. The semiconductor dies are electrically interconnected within the power module to form part of a power electronics circuit. The base region of the lead frame is electrically isolated from the power electronics circuit by the insulating body of the substrates. The leads of the lead frame protrude from one or more side faces of the mold compound and form terminals of the power module.

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

Abstract: A power electronic system includes a semiconductor module that includes a power electronic substrate having opposite first and second sides, power semiconductor die arranged over the second side of the substrate, and an encapsulation encapsulating the power semiconductor dies. The first side of the power electronic substrate is at least partially exposed from a first side of the encapsulation. The semiconductor module is arranged over an exterior surface of a wall of a cooler configured for fluidic cooling, such that the first side of the power electronic substrate faces the wall. The cooler includes cooling structures arranged on an interior surface of the wall. A first portion of the wall directly below the power electronic substrate has a first wall thickness and a second portion of the wall laterally next to the first portion has a second wall thickness, the first wall thickness being greater than the second wall thickness.

Abstract: A power module includes a metal frame a metal frame having first and second device attach pads, first and second semiconductor packages each having an encapsulant body and a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages, wherein the first semiconductor package is mounted on the first device attach pad, wherein the second semiconductor package is mounted on the second device attach pad, and wherein terminals from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.

Abstract: A substrate arrangement includes: a first metallization layer, nanowires arranged on a surface of the first metallization layer; and a component arranged on the first metallization layer such that a first subset of the nanowires is arranged between the first metallization layer and the component. The nanowires are evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer. Each nanowire includes first and second ends. The first end of each nanowire is inseparably connected to the surface of the first metallization layer. The second end of each nanowire of the first subset is inseparably connected to a surface of one of the component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the component. There are fewer nanowires in the first subset of nanowires than there are total nanowires.

Abstract: A power semiconductor package comprises a leadframe comprising a first die pad, a second die pad and a plurality of external contacts. The first and second die pads are separated by a first gap. A power semiconductor die is arranged on and electrically coupled to a first side of the first die pad. A diode is arranged on and electrically coupled to a first side of the second die pad. A molded body encapsulates the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides. A second side of the first die pad is exposed from the second side of the molded body. A second side of the second die pad is completely covered by an electrically insulating material.

Abstract: A power module includes a metal frame having a first and second device attach pads, first and second semiconductor packages each having an encapsulant body, a die pad exposed at a lower surface of the encapsulant body, a plurality of leads protruding out from the encapsulant body, and a potting compound that encapsulates both of the first and second semiconductor packages and partially covers the metal frame. The first semiconductor package is mounted on the metal frame such that the die pad of the first semiconductor package faces and electrically contacts the first device attach pad. The second semiconductor package is mounted on the metal frame such that the die pad of the second semiconductor package faces and electrically contacts the second device attach pad. The plurality of leads from each of the first and second semiconductor packages are electrically accessible from outside of the potting compound.

Abstract: A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component.

Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.