Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.

Abstract: Requester circuitry 4 issues an access request specifying a target physical address (PA) and a target physical address space (PAS) identifier identifying a target PAS. Prior to a point of physical aliasing (PoPA), a pre-PoPA memory system component 24, 8 treats aliasing PAs from different PASs which actually correspond to the same memory system resource as if they correspond to different memory system resources. A post-PoPA memory system component 6 treats the aliasing PAs as referring to the same memory system resource. When the target PA and target PAS of a read-if-hit-pre-PoPA request hit in a pre-PoPA cache 24, a data response is returned to the requester circuitry 4. If the read-if-hit-pre-PoPA request misses in the pre-PoPA cache 24, a no-data response is returned. The read-if-hit-pre-PoPA request is safe to issue speculatively while waiting for security checks to be performed, improving performance.

Abstract: An apparatus is described that has processing circuitry for performing operations, and a communication path employed by the processing circuitry to access a first memory. Switch circuitry, when activated, is connected to the communication path. The processing circuitry issues access commands specifying addresses to be accessed, where each address is mapped to location in a memory system in accordance with a system address map. The memory system comprises at least the first memory and a second memory. When in a particular mode, the processing circuitry performs operations that require access to only a subset of the locations provided in the first memory. The switch circuitry is arranged, whilst the processing circuitry is in the particular mode, to be activated in order to intercept the access commands issued over the communication path that specify addresses mapped by the system address map to locations within the subset of locations.

Abstract: A data processing system is provided comprising a cache system configured to transfer data between a processor and memory system. The cache system comprises a cache. When a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the block of data is stored into a group of one or more cache lines of the cache and the associated compression metadata for the compressed block of data is provided as separate side band data.

Abstract: Circuitry comprises a transaction interface to receive a data handling transaction from an upstream device, the data handling transaction defining a target virtual memory address in a virtual memory address space; translation circuitry to access a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space; the translation circuitry being configured to initiate handling of the data handling transaction by a downstream device according to a target physical memory address mapped from the target virtual memory address when the set of address mappings includes an address mapping for the target virtual memory address, and to provide a transaction response to the transaction interface indicating a fault condition when the set of address mappings fails to provide an address mapping for the target virtual memory address; and control circuitry to receive a memory region request from the upstream device, requesting that a memory region in the virtual memory

Abstract: Memory management apparatus comprises input circuitry to receive a translation request defining a first memory address within a first memory address space; prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address; control circuitry to initiate processing of the predicted second memory address; translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address.

Abstract: A memory system component comprises transaction handling circuitry to receive memory access transactions. Each memory access transaction specifies at least: an issuing domain identifier which indicates an issuing security domain specified by an issuing master device for the memory access transaction, where the issuing security domain is one of a plurality of security domains; a target address; and a security check indication which indicates whether it is already known that the memory access transaction would pass a security checking procedure. The security checking procedure determines whether the memory access transaction indicating said issuing security domain is authorised to access the target address, based on control data indicative of which of the plurality of security domains are allowed to access the target address. The memory system component comprises control circuitry to determine, on the basis of the security check indication, whether the security checking procedure still needs to be performed.

Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

Abstract: Circuitry comprises a transaction interface to receive a data handling transaction from an upstream device, the data handling transaction defining a target virtual memory address in a virtual memory address space; translation circuitry to access a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space; the translation circuitry being configured to initiate handling of the data handling transaction by a downstream device according to a target physical memory address mapped from the target virtual memory address when the set of address mappings includes an address mapping for the target virtual memory address, and to provide a transaction response to the transaction interface indicating a fault condition when the set of address mappings fails to provide an address mapping for the target virtual memory address; and control circuitry to receive a memory region request from the upstream device, requesting that a memory region in the virtual memory

Abstract: Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.

Abstract: An apparatus has an address translation cache (12, 16) having a number of cache entries (40) for storing address translation data which depends on one or more page table entries of page tables. Control circuitry (50) is responsive to an invalidation request specifying address information to perform an invalidation lookup operation to identify at least one target cache entry to be invalidated. The target cache entry is an entry for which the corresponding address translation data depends on at least one target page table entry corresponding to the address information. The control circuitry (50) selects one of a number of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicating the page size of the target page table entry. The different invalidation lookup modes correspond to different ways of identifying the target cache entry based on the address information.

Abstract: A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

Abstract: An apparatus has an address translation cache with entries for storing address translation data. Partition configuration storage circuitry stores multiple sets of programmable configuration data each corresponding to a partition identifier identifying a corresponding software execution environment or master device and specifying a corresponding subset of entries of the cache. In response to a translation lookup request specifying a target address and a requesting partition identifier, control circuitry triggers a lookup operation to identify whether the target address hits or misses in the corresponding subset of entries specified by the set of partition configuration data for the requesting partition identifier.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: A data processing apparatus (2) has a number of devices (4) having a normal state and a quiescent state. Transition sequencing circuitry (70) controls a sequential state transition process for transitioning each of the devices (4) in turn between the normal state and the quiescent state. For each device, the transition sequencing circuitry (70) controls the transition based on at least one preference indication transmitted from that device (4) providing an indication of a preference to operating the normal state or the quiescent state.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: There is described a method and data processing apparatus configured to translate a virtual address into a physical address, the virtual address comprising an offset for a memory page, an index and a tag with the memory page having a variable size.

Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.

Abstract: An apparatus has an address translation cache with entries for storing address translation data. Partition configuration storage circuitry stores multiple sets of programmable configuration data each corresponding to a partition identifier identifying a corresponding software execution environment or master device and specifying a corresponding subset of entries of the cache. In response to a translation lookup request specifying a target address and a requesting partition identifier, control circuitry triggers a lookup operation to identify whether the target address hits or misses in the corresponding subset of entries specified by the set of partition configuration data for the requesting partition identifier.