Patents by Inventor Andrew Brookfield Swaine

Andrew Brookfield Swaine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8176366
    Abstract: A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: May 8, 2012
    Assignee: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Thomas Sean Houlihane, Sheldon James Woodhouse, Michael John Williams
  • Publication number: 20120110387
    Abstract: A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream.
    Type: Application
    Filed: December 29, 2011
    Publication date: May 3, 2012
    Applicant: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Thomas Sean Houlihane, Sheldon James Woodhouse, Michael John Williams
  • Publication number: 20120030499
    Abstract: Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount.
    Type: Application
    Filed: June 28, 2011
    Publication date: February 2, 2012
    Applicant: ARM Limited
    Inventor: Andrew Brookfield Swaine
  • Patent number: 8099635
    Abstract: A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: January 17, 2012
    Assignee: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Thomas Sean Houlihane
  • Publication number: 20110320651
    Abstract: A data processing apparatus is provided comprising a buffer for buffering data contained in a data stream generated by a data stream generator and received by a data stream receptor. Buffer occupancy tracking circuitry is provided and configured to maintain a high buffer utilisation value providing an indication of a high buffer occupation level for a given time period during utilisation of the buffer. Alternatively, in an apparatus where the buffer is implemented in dedicated memory, the buffer occupancy tracking circuitry is configured to store a programmable buffer size limit controlling a maximum allowable buffer storage capacity.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: ARM LIMITED
    Inventors: Serge Henri Poublan, Andrew Brookfield Swaine
  • Publication number: 20110231461
    Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M?N. The data processing apparatus comprises a selection storage unit configured to store N+1 identifier selection bits, wherein a position of a marker bit in the N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers are defined by a base identifier and 2M?1 identifiers incrementally following that base identifier. N?M bits of the N+1 identifier selection bits form N?M most significant bits of the base identifier, and M trailing zeroes form the M least significant bits of the base identifier.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 22, 2011
    Applicant: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Michael John Williams
  • Patent number: 8001428
    Abstract: A data processing apparatus is provided with packing circuitry 130 arranged to receive said source data elements from said trace data receiver and applies a packing protocol to said source data elements to pack data of source data elements of a source trace stream into a packed trace data stream for supply to trace accepting circuitry in a format comprising acceptance data elements. The acceptance data elements have a bit-length that is not a factor of the source data element bit-length. In some arrangements the source data elements are non byte-sized data elements. In alternative arrangements, the packing circuitry packs a first positive integer number of source data elements into a data chunk comprising a second, different positive integer number of acceptance data elements.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: August 16, 2011
    Assignee: ARM Limited
    Inventors: Edmond John Simon Ashfield, Andrew Brookfield Swaine
  • Patent number: 7937626
    Abstract: A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: May 3, 2011
    Assignee: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Thomas Sean Houlihane
  • Publication number: 20110029823
    Abstract: A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles.
    Type: Application
    Filed: October 6, 2010
    Publication date: February 3, 2011
    Applicant: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Thomas Sean Houlihane
  • Patent number: 7870437
    Abstract: A data processing apparatus is provided, comprising monitored circuitry for performing activities, trace circuitry for producing a stream of trace elements representative of at least some of these activities, and detection circuitry for detecting the occurrence of a predetermined subset of the activities for which the trace circuitry is producing trace elements. When an activity in that predetermined subset of activities is detected a timing indication is added to the stream of trace elements. Hence, the valuable trace bandwidth- may be preserved, by limiting the trace elements for which a timing indication is added into the trace stream to a predetermined subset of the activities for which trace elements are generated, and the valuable global or relative timing accuracy of those activities represented in the trace stream is retained, without flooding the trace stream with timing indications.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: January 11, 2011
    Assignee: ARM Limited
    Inventors: Andrew Brookfield Swaine, Richard Roy Grisenthwaite, Michael John Williams
  • Publication number: 20100257510
    Abstract: A data processing apparatus having one or more trace data sources is provided in which the trace data sources operate to generate respective streams of trace data. At least one of said trace data sources comprises a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. The synchronization marker identifies a synchronization position in the trace data stream. A controller is coupled to the synchronization marker generator, and operates to initiate the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator with respect to trace data flow.
    Type: Application
    Filed: April 3, 2009
    Publication date: October 7, 2010
    Applicant: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Thomas Sean Houlihane, Sheldon James Woodhouse, Michael John Williams
  • Patent number: 7730545
    Abstract: Test access to an integrated circuit 2 is controlled by the use of test access enabling keys. A plurality of different test access enabling levels may be supported corresponding to different keys. The test access control may be performed by dedicated hardware or software executing a secure privilege mode.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: June 1, 2010
    Assignee: ARM Limited
    Inventors: George James Milne, Andrew Brookfield Swaine, Donald Felton
  • Publication number: 20090313507
    Abstract: A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Inventors: Andrew Brookfield Swaine, Michael John Williams, David Kevin Hart, Andrew Christopher Rose
  • Publication number: 20090193297
    Abstract: A data processing system 1 has a processor core 2 which is programmable to act as one of a plurality of virtual machines each identified by a virtual machine identifier, each virtual machine acting in one of a plurality of contexts each identified by a context identifier, each context executing a sequence of program instructions, each program instruction having one or more associated memory addresses. The data processing system has diagnostic circuitry 10 for performing diagnostic operations on the processor core. Diagnostic control circuitry 12 is provided which is responsive to current values of the virtual machine identifier, the context identifier and at least one of the one or more associated memory addresses to trigger the diagnostic circuitry 10 to perform diagnostic operations.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 30, 2009
    Applicant: ARM LIMITED
    Inventors: Michael John Williams, Richard Roy Grisenthwaite, Andrew Brookfield Swaine, John Michael Horley
  • Publication number: 20090132863
    Abstract: A data processing apparatus is provided with packing circuitry 130 arranged to receive said source data elements from said trace data receiver and applies a packing protocol to said source data elements to pack data of source data elements of a source trace stream into a packed trace data stream for supply to trace accepting circuitry in a format comprising acceptance data elements. The acceptance data elements have a bit-length that is not a factor of the source data element bit-length. In some arrangements the source data elements are non byte-sized data elements. In alternative arrangements, the packing circuitry packs a first positive integer number of source data elements into a data chunk comprising a second, different positive integer number of acceptance data elements.
    Type: Application
    Filed: October 27, 2008
    Publication date: May 21, 2009
    Applicant: ARM LIMITED
    Inventors: Edmond John Simon Ashfield, Andrew Brookfield Swaine
  • Publication number: 20090125756
    Abstract: A data processing apparatus is provided, comprising monitored circuitry for performing activities, trace circuitry for producing a stream of trace elements representative of at least some of these activities, and detection circuitry for detecting the occurrence of a predetermined subset of the activities for which the trace circuitry is producing trace elements. When an activity in that predetermined subset of activities is detected a timing indication is added to the stream of trace elements. Hence, the valuable trace bandwidth- may be preserved, by limiting the trace elements for which a timing indication is added into the trace stream to a predetermined subset of the activities for which trace elements are generated, and the valuable global or relative timing accuracy of those activities represented in the trace stream is retained, without flooding the trace stream with timing indications.
    Type: Application
    Filed: November 14, 2007
    Publication date: May 14, 2009
    Applicant: ARM LIMITED
    Inventors: Andrew Brookfield Swaine, Richard Roy Grisenthwaite, Michael John Williams
  • Publication number: 20090006934
    Abstract: A data processing apparatus 2 is provided including diagnostic mechanism 10, 12 and comparator circuitry 8. The comparator circuitry 8 is responsive to a signal indicative of execution of a block of program instructions to trigger any watchpoints or watch ranges within that block of program instructions. The relative ordering of the watchpoints or watch ranges is established by ordering characteristics associated therewith, such as programmable priority values, or an implicit ordering given by the storage location of the watchpoint or watch range.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Applicant: ARM Limited
    Inventors: John Michael Horley, Andrew Brookfield Swaine
  • Publication number: 20080235538
    Abstract: A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles.
    Type: Application
    Filed: February 26, 2008
    Publication date: September 25, 2008
    Applicant: ARM LIMITED
    Inventors: John Michael Horley, Andrew Brookfield Swaine, Thomas Sean Houlihane
  • Patent number: 7426659
    Abstract: A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: September 16, 2008
    Assignee: ARM Limited
    Inventors: Conrado Blasco Allue, Paul Kimelman, Andrew Brookfield Swaine, Richard Roy Grisenthwaite
  • Patent number: 7325168
    Abstract: A trace data formatter 30 assembles trace data frames 50. These trace data frames 50 include bytes which may either serve to carry a trace data source identifier ID or trace data. A system being traced has multiple trace data sources 12, 14, 16, 18 and when the trace data source which is generating the current trace data stream changes then a trace data source identifier ID is inserted within the trace data stream.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: January 29, 2008
    Assignee: ARM Limited
    Inventors: Daryl Wayne Bradley, Sheldon James Woodhouse, Andrew Brookfield Swaine