Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

Abstract: Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.

Abstract: A filter unit comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter unit has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

Abstract: A data processing apparatus (2) has a number of devices (4) having a normal state and a quiescent state. Transition sequencing circuitry (70) controls a sequential state transition process for transitioning each of the devices (4) in turn between the normal state and the quiescent state. For each device, the transition sequencing circuitry (70) controls the transition based on at least one preference indication transmitted from that device (4) providing an indication of a preference to operating the normal state or the quiescent state.

Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.

Abstract: There is described a method and data processing apparatus configured to translate a virtual address into a physical address, the virtual address comprising an offset for a memory page, an index and a tag with the memory page having a variable size.

Abstract: A data processing system 2 incorporates a translation buffer unit 24, 26, 28 and a translation control unit 30. The translation buffer unit responds to receipt of a memory access transaction for which translation data is unavailable in that translation buffer unit by issuing a request to the translation control unit to provide translation data for the memory access transaction. The translation control unit is responsive to disabling or enabling of address translation for a given type of memory access transaction to an issue invalidate command to all translation buffer units which may be holding translation data for that given type of memory access transaction.

Abstract: A data processing system 2 incorporates a translation buffer unit 24, 26, 28 and a translation control unit 30. The translation buffer unit responds to receipt of a memory access transaction for which translation data is unavailable in that translation buffer unit by issuing a request to the translation control unit to provide translation data for the memory access transaction. The translation control unit is responsive to disabling or enabling of address translation for a given type of memory access transaction to an issue invalidate command to all translation buffer units which may be holding translation data for that given type of memory access transaction.

Abstract: A data processing apparatus 2 includes bridge circuitry 14, 16, 18 which serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitry 18 which maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.

Abstract: Apparatus for data processing and a method of data processing are provided. Address translation storage stores address translations between first set addresses and second set addresses, and responds to a request comprising a first set address to return a response comprising a second set address if the required address translation is currently stored therein. If it is not the request is forwarded towards memory in a memory hierarchy. A pending request storage stores entries for received requests and in response to reception of the request, if a stored entry for a previous request indicates that the previous request has been forwarded towards the memory and an expected response to the previous request will provide the address translation, intercepts the request to delay its reception by the address translation storage. Bandwidth pressure on the address translation storage is thus relieved.

Abstract: A data processing apparatus 2 includes bridge circuitry 14, 16, 18 which serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitry 18 which maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.

Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M?N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

Abstract: A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.

Abstract: Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount.

Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M?N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M?N. The data processing apparatus comprises a selection storage unit configured to store N+1 identifier selection bits, wherein a position of a marker bit in the N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers are defined by a base identifier and 2M?1 identifiers incrementally following that base identifier. N?M bits of the N+1 identifier selection bits form N?M most significant bits of the base identifier, and M trailing zeroes form the M least significant bits of the base identifier.

Abstract: A data processing apparatus is provided comprising a buffer for buffering data contained in a data stream generated by a data stream generator and received by a data stream receptor. Buffer occupancy tracking circuitry is provided and configured to maintain a high buffer utilisation value providing an indication of a high buffer occupation level for a given time period during utilisation of the buffer. Alternatively, in an apparatus where the buffer is implemented in dedicated memory, the buffer occupancy tracking circuitry is configured to store a programmable buffer size limit controlling a maximum allowable buffer storage capacity.

Abstract: A data processing apparatus is provided including diagnostic mechanism and comparator circuitry. The comparator circuitry is responsive to a signal indicative of execution of a block of program instructions to trigger any watchpoints or watch ranges within that block of program instructions. The relative ordering of the watchpoints or watch ranges is established by ordering characteristics associated therewith, such as programmable priority values, or an implicit ordering given by the storage location of the watchpoint or watch range.

Abstract: A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream.

Abstract: A data processing system 1 has a processor core 2 which is programmable to act as one of a plurality of virtual machines each identified by a virtual machine identifier, each virtual machine acting in one of a plurality of contexts each identified by a context identifier, each context executing a sequence of program instructions, each program instruction having one or more associated memory addresses. The data processing system has diagnostic circuitry 10 for performing diagnostic operations on the processor core. Diagnostic control circuitry 12 is provided which is responsive to current values of the virtual machine identifier, the context identifier and at least one of the one or more associated memory addresses to trigger the diagnostic circuitry 10 to perform diagnostic operations.