Patents by Inventor Andrew Dale

Andrew Dale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120159004
    Abstract: A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card.
    Type: Application
    Filed: February 24, 2012
    Publication date: June 21, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lee Dale Cleveland, Seth David Lewis, Christopher William Mann, Andrew Dale Walls
  • Patent number: 8186900
    Abstract: A connector assembly comprising a housing and a tensile member disposed within the housing. The tensile member comprises first and second end portions. Each end portion sealingly engages the housing to form a hydraulic chamber therebetween. A first connector pivotally coupled to the first end portion. The axial position of the first connector relative to the housing is controlled by pressure within the hydraulic chamber.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: May 29, 2012
    Assignee: National-Oilwell, L.P.
    Inventors: Andrew Dale Riley, Randall Ferrain Weaver
  • Patent number: 8151051
    Abstract: A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: April 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lee Dale Cleveland, Seth David Lewis, Christopher William Mann, Andrew Dale Walls
  • Patent number: 8095691
    Abstract: Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: William Garrett Verdoorn, Jr., Andrew Dale Walls
  • Patent number: 8032816
    Abstract: An apparatus and method for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Carol Spanel, Andrew Dale Walls
  • Patent number: 8024524
    Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, James Chien-Chung Chen, Yu-Cheng Hsu, Matthew Joseph Kalos, Carol Spanel, Andrew Dale Walls
  • Publication number: 20110168014
    Abstract: A pump including a pressure compensated piston is disclosed. In some embodiments, the pump includes a piston with an annular body and an annular sealing element disposed radially outward of the annular body. The annular body has a radially-facing outer surface adjacent an inner surface of the sealing element and an axially-facing surface with an inlet port. A flowpath extends between the inlet port and the radially-facing outer surface of the annular body.
    Type: Application
    Filed: April 23, 2008
    Publication date: July 14, 2011
    Applicant: NATIONAL OILWELL VARCO, L. P.
    Inventors: Andrew Dale Riley, Jason Whaley
  • Patent number: 7971124
    Abstract: An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Carol Spanel, Andrew Dale Walls
  • Publication number: 20110066882
    Abstract: A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure.
    Type: Application
    Filed: September 16, 2009
    Publication date: March 17, 2011
    Applicant: International Business Machines Corporation
    Inventors: Andrew Dale Walls, Daniel Frank Moertl
  • Publication number: 20110024586
    Abstract: A material dispensing system for hanging from a support is disclosed. The material dispensing system may contain a hanging member that includes an arm and an extension member slidably mounted on the arm. The arm includes a proximal end and a distal end. The rotatable attachment is a pivot point for the hanging member to rotate under or into the material dispenser. The extension member includes a retaining element to engage a support structure or a spindle of the paper roll holder. The material dispenser may include a base defining a cavity to store the hanging member which is rotatable into the cavity for storage. The hanging member may also have a proximal end rotatably connected to the material dispenser, and a distal end including a retaining element, wherein the retaining element is rotatable through an angle of at least about 90 degrees.
    Type: Application
    Filed: September 29, 2009
    Publication date: February 3, 2011
    Inventors: Andrew Dale Brinkdopke, Ryan Leslie Fulscher, Robert Samuel Schlaupitz
  • Publication number: 20110024585
    Abstract: Generally, a mounting bracket for mounting a mountable object is disclosed. The mounting bracket includes a baseplate has a substantially flat mounting surface and an opposite outward-facing surface. A ledge extends a first distance from the outward-facing surface to support the mountable object. A mounting bracket locking component adapted to frictionally engage a mountable object locks the mountable object in place. Additionally, a stabilizing member extending a second distance from the outward-facing surface contacts the mountable object to help limit movement of the object during use. The mounting bracket may be used with a material dispenser in a wall mountable material dispensing system. The wall mountable material dispensing system may be packaged as a kit wherein the mounting bracket is packaged within the material dispenser.
    Type: Application
    Filed: September 29, 2009
    Publication date: February 3, 2011
    Inventors: Andrew Dale Brinkdopke, Ryan Leslie Fulscher, Robert Samuel Schlaupitz, Christine Marie Cowell, David James Wilks, Elizabeth Oriel Bradley
  • Patent number: 7870417
    Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Stephen L. Blinick, Cheng-Chung Song, Carol Spanel, Andrew Dale Walls
  • Publication number: 20100332749
    Abstract: A computational device allocates a plurality of solid state disks to a plurality of redundant array of independent disk (RAID) ranks, wherein a different solid state disk is absent in each RAID rank of the plurality of RAID ranks. The computational device determines at least one selected solid state disk from the plurality of solid state disks, wherein the at least one selected solid state disk is estimated to have undergone a greater amount of wear in comparison to other solid state disks in the plurality of solid state disks. Relatively more data and parity information is written to those RAID ranks in which the at least one selected solid state disk is absent in comparison to those RAID ranks in which the at least one selected solid state disk is present.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Thomas Benhase, Andrew Dale Walls
  • Publication number: 20100274965
    Abstract: A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card.
    Type: Application
    Filed: April 23, 2009
    Publication date: October 28, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lee Dale Cleveland, Seth David Lewis, Christopher William Mann, Andrew Dale Walls
  • Publication number: 20100268986
    Abstract: Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 21, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Garrett Verdoorn, JR., Andrew Dale Walls
  • Patent number: 7789161
    Abstract: A seal assembly, for sealing between a stationary conduit and a rotating conduit, comprises an upper gland assembly, a washpipe, and a lower gland assembly. The upper gland assembly is operable to engage the stationary conduit. A washpipe partially disposed within the upper gland assembly. An upper seal member is disposed within the upper gland assembly around a periphery of the washpipe. An upper packing ring is engaged with the upper gland assembly so as to compress the upper seal member into sealing engagement with the washpipe. A lower gland assembly is disposed about the washpipe and operable to engage the rotating conduit. A lower seal member is disposed within the lower gland assembly and is compressed into sealing engagement with the washpipe by a lower packing ring that is engaged with the lower gland assembly. The engagement of the packing rings with their respective gland assemblies is independent of the engagement of the gland assemblies and the conduits.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: September 7, 2010
    Assignee: National Oilwell Varco, L.P.
    Inventors: Andrew Dale Riley, Randall Ferrain Weaver
  • Patent number: 7787490
    Abstract: Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael Joseph Azevedo, Andrew Dale Walls
  • Patent number: 7783813
    Abstract: Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: William Garrett Verdoorn, Jr., Andrew Dale Walls
  • Publication number: 20100161902
    Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.
    Type: Application
    Filed: August 7, 2009
    Publication date: June 24, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Thomas Benhase, James Chien-Chung Chen, Yu-Cheng Hsu, Matthew Joseph Kalos, Carol Spanel, Andrew Dale Walls
  • Patent number: D630939
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 18, 2011
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Timothy James Peters, Andrew Dale Brinkdopke, Elizabeth Oriel Bradley, Robert Samuel Schlaupitz, Meghan Marie McGuire, Martin John Behling, II