Abstract: A pump cylinder liner apparatus includes a replaceable sleeve captured between two cylinder hull portions that are releasably coupled to allow access to the sleeve for replacement. An elastomeric material or tube may be disposed between the sleeve and the two coupled hull portions for radial compressive pre-loading of the sleeve upon assembly and during operation.

Abstract: Non-destructive imaging of an object. An imaging head supported on a rotatable arm samples an electric field scattered by the object at a plurality of locations as the arm rotates about a central axis, with the locations corresponding to a defined spatial domain located remotely from the object. One or more processors execute computer-readable instructions for controlling rotation of the arm and generating a multi-dimensional profile representative of the object in the defined spatial domain based on the sampling.

Abstract: A reciprocating pump including a piston is disclosed. In some embodiments, the piston includes an annular hub, a flexible sealing element coupled to an outer surface of the hub, and a sleeve seated on the outer surface of the hub adjacent the sealing element. The sleeve is axially moveable relative to the hub to compress the sealing element. The sealing element includes a lip, which is displaced radially outward when the sleeve compresses the sealing element.

Abstract: A valve cover assembly for a pump. In an embodiment, the valve cover assembly comprises a first cylindrical member having a central axis and a first throughbore. In addition, the valve cover assembly comprises a second cylindrical member coaxially disposed within the first throughbore and rotatable relative to the first cylindrical member about the central axis between a first position and a second position. In the first position, the second cylindrical member is axially translatable relative to the first cylindrical member. In the second position, the second cylindrical member is axially fixed relative to the first cylindrical member.

Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

Abstract: An apparatus, system, and method are disclosed for mandatory end to end integrity checking. The apparatus includes a compatibility module configured to monitor data from a source and verify integrity information compatibility with a standard, and an integrity module configured to wrap the data from the source with additional integrity information. The system includes a source configured to send data over a network, a target configured to receive data over the network, the apparatus, a main memory module, a storage controller, and a storage device. The method includes monitoring data from a source, verifying integrity information compatibility with a standard, and wrapping the data from the source with additional integrity information.

Abstract: A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold.

Abstract: Apparatus and method for applying radial compressive stress pre-loading to a cylinder liner. A cylinder housing is attached to a pump, and a cylinder liner is disposed within the cylinder housing. A fluid inlet in fluid communication with the annular space between the cylinder housing and cylinder liner is disposed on the cylinder housing. The annular space is filled with pressurizing fluid through the fluid inlet, which creates radial compressive stress pre-loading on the cylinder liner.

Abstract: A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

Abstract: Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Abstract: An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.

Abstract: An apparatus and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.

Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold.

Abstract: An apparatus, system, and method are disclosed for data error checking and recovery in a data storage device. A redundancy check module creates a redundancy check for data on a data storage device in a SCSI End-to-End Checking Standard environment and a redundancy check storage module stores the redundancy check in a guard associated with the data.

Abstract: Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

Abstract: Apparatus and methods for constructing a valve comprising a sealing member and a hollow ball operable to sealingly engage the sealing member. A guide housing disposed about said hollow ball and does not constrain rotation of said hollow ball. A spring is disposed between the hollow ball and the guide housing so as to bias the hollow ball into sealing engagement with the sealing member. The hollow ball is constructed from two unequal sized portions and may comprise a hollow, spherical body having an aperture and a plug sized so as to closely fit within the aperture.