Patents by Inventor Andrew K. Chan

Andrew K. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6101074
    Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 8, 2000
    Assignee: QuickLogic Corporation
    Inventors: James M. Apland, Andrew K. Chan
  • Patent number: 6097651
    Abstract: A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: August 1, 2000
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, James M. Apland, Ket-Chong Yap
  • Patent number: 6078191
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: June 20, 2000
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5989943
    Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
    Type: Grant
    Filed: December 8, 1989
    Date of Patent: November 23, 1999
    Assignee: QuickLogic Corporation
    Inventors: Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas, Hua-Thye Chua, Andrew K. Chan, John M. Birkner
  • Patent number: 5986468
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: November 16, 1999
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5898776
    Abstract: A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: April 27, 1999
    Assignee: QuickLogic Corporation
    Inventors: James M. Apland, David D. Eaton, Andrew K. Chan
  • Patent number: 5828538
    Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: October 27, 1998
    Assignee: QuickLogic Corporation
    Inventors: James M. Apland, Andrew K. Chan
  • Patent number: 5780919
    Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: July 14, 1998
    Assignee: QuickLogic Corporation
    Inventors: Hua-Thye Chua, Andrew K. Chan, John M. Birkner, Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas
  • Patent number: 5726586
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: March 10, 1998
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5717230
    Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: February 10, 1998
    Assignee: QuickLogic Corporation
    Inventors: Hua-Thye Chua, Andrew K. Chan, John M. Birkner, Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas
  • Patent number: 5661412
    Abstract: Critical programmed reliability of a metal-to-metal amorphous silicon antifuse is a function of programming current, operating current and total programming time. The time required to program a field programmable gate array is reduced by classifying antifuses to be programmed into three or more classes according to the amount of programming time required to achieve critical programmed reliability under programming current and operating current conditions. Each of these classes of antifuses is programmed with near the minimum programming time required to program every antifuse in the class to critical reliability. In this way, large numbers of antifuses are not programmed with significantly greater amounts of programming time than are actually required to program them to critical reliability. The time required to program the field programmable gate array is therefore reduced. Techniques for obtaining critical reliability data used in classifying antifuses are also disclosed.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: August 26, 1997
    Assignee: QuickLogic Corporation
    Inventors: Amarpreet S. Chawla, Richard J. Wong, Andrew K. Chan
  • Patent number: 5594364
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: January 14, 1997
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5587669
    Abstract: In a field programmable gate array, a plurality of wire segments extend parallel to each other between two logic cells. Some of the wire segments extend to logic cell inputs and others to logic cell outputs. A power wire extends perpendicular to the wire segments and crosses each of the wire segments. Antifuses are disposed to couple the input wire segments to the power wire but no antifuses are disposed between the output wire segments and the power wire.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: December 24, 1996
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua T. Chua
  • Patent number: 5502315
    Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: March 26, 1996
    Assignee: QuickLogic Corporation
    Inventors: Hua-Thye Chua, Andrew K. Chan, John M. Birkner, Ralph G. Whitten, Richard L. Bechtel, Mammen Thomas
  • Patent number: 5471154
    Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: November 28, 1995
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Andrew K. Chan
  • Patent number: 5430390
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: July 4, 1995
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5416367
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: May 16, 1995
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua T. Chua, William D. Cox
  • Patent number: 5397939
    Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.
    Type: Grant
    Filed: July 20, 1993
    Date of Patent: March 14, 1995
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Andrew K. Chan
  • Patent number: 5396127
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: March 7, 1995
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, Hua-Thye Chua
  • Patent number: 5302546
    Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: April 12, 1994
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Andrew K. Chan