Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.

Abstract: A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

Abstract: Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Abstract: A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.

Abstract: An apparatus comprising a substrate, a first nanosheet device located on the substrate, and a second nanosheet device located on the substrate, wherein the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device, wherein the at least one first gate has a first width. At least one second gate located on the second nanosheet device, wherein the at least one second gate has a second width, wherein the first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device, wherein the diffusion break prevents the first nanosheet device from contacting the second nanosheet device, wherein the diffusion break has a third width, wherein the third width is larger than the first width and the second width.

Abstract: A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.

Abstract: A semiconductor nanosheet device including semiconductor channel layers vertically aligned and stacked one on top of another, separated by a work function metal, and a second layer between two first layers, the second layer and two first layers between the semiconductor channel layers and a substrate. A semiconductor device including a lower first layer, a second layer, and a source drain region between a first set of semiconductor channel layers vertically aligned and stacked one on top of another, and a second set of semiconductor channel layers. A method including forming a stack sacrificial layer, a stack of nanosheet layers, forming a cavity by removing the stack sacrificial layer, and simultaneously forming a first layer on an upper surface of the stack sacrificial layer, on vertical side surfaces of the set of sacrificial gates, and an upper first layer and a lower first layer in a portion of the cavity.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; a transistor stack structure formed on the semiconductor substrate, the transistor stack structure including a first FET and a second FET, where the first FET is a different polarity than the second FET; a first source-drain epitaxial layer of the first FET formed directly on the substrate adjacent to the first FET; and a second source-drain epitaxial layer of the second FET formed on the substrate adjacent to the second FET, wherein a bottom dielectric isolation layer is formed between the substrate and the second epitaxial layer.

Abstract: A conformally deposited metal liner used for forming discrete, wrap-around contact structures is localized between pairs of gate structures and below the tops of the gate structures. Block mask patterning is employed to protect transistors over active regions of a substrate while portions of the metal liner between active regions are removed. A chamfering technique is employed to selectively remove further portions of the metal liner within the active regions. Metal silicide liners formed on the source/drain regions using the conformally deposited metal liner are electrically connected to source/drain contact metal following the deposition and patterning of a dielectric layer and subsequent metallization.

Abstract: A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.

Abstract: A conformally deposited metal liner used for forming discrete, wrap-around contact structures is localized between pairs of gate structures and below the tops of the gate structures. Block mask patterning is employed to protect transistors over active regions of a substrate while portions of the metal liner between active regions are removed. A chamfering technique is employed to selectively remove further portions of the metal liner within the active regions. Metal silicide liners formed on the source/drain regions using the conformally deposited metal liner are electrically connected to source/drain contact metal following the deposition and patterning of a dielectric layer and subsequent metallization.

Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Abstract: Semiconductor devices and methods of forming the same include recessing sacrificial layers in a stack of alternating sacrificial layers and channel layers using a first etch to form curved recesses at sidewalls of each sacrificial layer in the stack, with tails of sacrificial material being present at a top and bottom of each curved recess. Dielectric plugs are formed that each partially fill a respective curved recess, leaving exposed at least a portion of each tail of sacrificial material. The tails of sacrificial material are etched back using a second etch to expand the recesses. Inner spacers are formed in the expanded recesses.

Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Abstract: Semiconductor devices and methods of forming the same include recessing sacrificial layers in a stack of alternating sacrificial layers and channel layers using a first etch to form curved recesses at sidewalls of each sacrificial layer in the stack, with tails of sacrificial material being present at a top and bottom of each curved recess. Dielectric plugs are formed that each partially fill a respective curved recess, leaving exposed at least a portion of each tail of sacrificial material. The tails of sacrificial material are etched back using a second etch to expand the recesses. Inner spacers are formed in the expanded recesses.

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.