Patents by Inventor Andrew M. Greene

Andrew M. Greene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fin Cut to Prevent Replacement Gate Collapse on STI
    Publication number: 20200219874
    Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.
    Type: Application
    Filed: March 3, 2020
    Publication date: July 9, 2020
    Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre
  • METHOD OF FIN OXIDATION BY FLOWABLE OXIDE FILL AND STEAM ANNEAL TO MITIGATE LOCAL LAYOUT EFFECTS
    Publication number: 20200203214
    Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.
    Type: Application
    Filed: March 3, 2020
    Publication date: June 25, 2020
    Inventors: Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu, Reinaldo Vega
  • Gate cut in RMG
    Patent number: 10692990
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • GATE CUT DEVICE FABRICATION WITH EXTENDED HEIGHT GATES
    Publication number: 20200194563
    Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer has an internal structure that is the result of a thermal oxidation process and has a higher quality than an internal structure of the first dielectric layer. A gate stack is positioned through the first and second dielectric layers.
    Type: Application
    Filed: February 21, 2020
    Publication date: June 18, 2020
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • Fin isolation to mitigate local layout effects
    Patent number: 10685866
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Gen Tsutsui, Andrew M. Greene, Dechao Guo, Huiming Bu, Robert Robison, Veeraraghavan S. Basker, Reinaldo Vega
  • Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)
    Patent number: 10672910
    Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Ruqiang Bao, Michael P. Belyansky, Andrew M. Greene, Gen Tsutsui
  • Gate cut with integrated etch stop layer
    Patent number: 10665589
    Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 26, 2020
    Assignee: Tessera, Inc.
    Inventors: Marc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
  • Gate cut device fabrication with extended height gates
    Patent number: 10658473
    Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a flat, non-recessed top surface. A gate stack passes vertically through the first and second dielectric layers to contact the source and drain regions and an underlying substrate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects
    Patent number: 10658224
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu, Reinaldo Vega
  • GATE CUT WITH INTEGRATED ETCH STOP LAYER
    Publication number: 20200152628
    Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 14, 2020
    Inventors: Marc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
  • Gate cut in RMG
    Patent number: 10644129
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • Gate height control and ILD protection
    Patent number: 10629699
    Abstract: Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, John R. Sporre, Stan Tsai, Ruilong Xie
  • Gate cut using selective deposition to prevent oxide loss
    Patent number: 10622482
    Abstract: Semiconductor devices include a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric line is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric line. A top surface of the interlayer dielectric between the gate stack and the dielectric line is not recessed.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, Ekmini Anuja De Silva, Siva Kanakasabapathy
  • Fin cut to prevent replacement gate collapse on STI
    Patent number: 10622352
    Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre
  • FinFET gate cut after dummy gate removal
    Patent number: 10600868
    Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 24, 2020
    Assignee: Tessera, Inc.
    Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
  • Additive core subtractive liner for metal cut etch processes
    Patent number: 10600884
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • FIN ISOLATION TO MITIGATE LOCAL LAYOUT EFFECTS
    Publication number: 20200083088
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Huimei Zhou, Gen Tsutsui, Andrew M. Greene, Dechao Guo, Huiming Bu, Robert Robison, Veeraraghavan S. Basker, Reinaldo Vega
  • ADDITIVE CORE SUBTRACTIVE LINER FOR METAL CUT ETCH PROCESSES
    Publication number: 20200083349
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P.V. Seshadri, Rajasekhar Venigalla
  • GATE CUT DEVICE FABRICATION WITH EXTENDED HEIGHT GATES
    Publication number: 20200083334
    Abstract: Methods of forming semiconductor devices include forming a lower dielectric layer, to a height below a height of a dummy gate hardmask disposed across multiple device regions, by forming a dielectric fill to the height of a dummy gate and etching the dielectric fill back. A dummy gate structure includes the dummy gate and the dummy gate hardmask. A protective layer is formed on the dielectric layer to the height of the dummy gate hardmask. The dummy gate hardmask is etched back to expose the dummy gate.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • ADDITIVE CORE SUBTRACTIVE LINER FOR METAL CUT ETCH PROCESSES
    Publication number: 20200083350
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P.V. Seshadri, Rajasekhar Venigalla