Patents by Inventor Andrew M. Hawryluk

Andrew M. Hawryluk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140021826
    Abstract: A betavoltaic power source for transportation devices and applications is disclosed, wherein the device having a stacked configuration of isotope layers and energy conversion layers. The isotope layers have a half-life of between about 0.5 years and about 5 years and generate radiation with energy in the range from about 15 keV to about 200 keV. The betavoltaic power source is configured to provide sufficient power to operate the transportation device over its useful lifetime.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 23, 2014
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk
  • Publication number: 20130330844
    Abstract: Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 ?s to about 100 ?s. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 12, 2013
    Applicant: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Serguei Anikitchev
  • Patent number: 8592309
    Abstract: Methods of performing laser spike annealing (LSA) in forming gallium nitride (GaN) light-emitting diodes (LEDs) as well as GaN LEDs formed using LSA are disclosed. An exemplary method includes forming atop a substrate a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method also includes performing LSA by scanning a laser beam over the p-GaN layer. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: November 26, 2013
    Assignee: Ultratech, Inc.
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Publication number: 20130278109
    Abstract: A betavoltaic power source for mobile devices and mobile applications includes a stacked configuration of isotope layers and energy conversion layers. The isotope layers have a half-life of between about 0.5 years and about 5 years and generate radiation with energy in the range from about 15 keV to about 200 keV. The betavoltaic power source is configured to provide sufficient power to operate the mobile device over its useful lifetime.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 24, 2013
    Applicant: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk
  • Publication number: 20130267096
    Abstract: Systems for and methods of laser-enhanced plasma processing of semiconductor materials are disclosed. The method includes supporting a semiconductor material in a processing chamber interior and subjecting the semiconductor material to a plasma process. The method also includes simultaneously heating the wafer surface with a laser beam through a window in the processing chamber to increase the reaction rate of the plasma process. Other methods include performing laser heating of the semiconductor material before or after the plasma process but while the semiconductor material resides in the same chamber interior.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Inventors: Andrew M. Hawryluk, Arthur W. Zafiropoulo
  • Patent number: 8460959
    Abstract: Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing having a time duration of 10 seconds or faster. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: June 11, 2013
    Assignee: Ultratech, Inc.
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Publication number: 20130044301
    Abstract: A programmable illuminator for a photolithography system includes a light source, a first optical system having a light uniformizing element, a programmable micro-mirror device, and a second optical system that forms an illumination field that illuminates a reticle. The programmable micro-mirror device can be configured to perform shutter and edge-exposure-blocking functions that have previously required relatively large mechanical devices. Methods of improving illumination field uniformity using the programmable illuminator are also disclosed.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Inventors: Borislav Zlatanov, Andrew M. Hawryluk
  • Patent number: 8309474
    Abstract: Systems and methods for performing ultrafast laser annealing in a manner that reduces pattern density effects in integrated circuit manufacturing are disclosed. The method includes scanning at least one first laser beam over the patterned surface of a substrate. The at least one first laser beam is configured to heat the patterned surface to a non-melt temperature Tnonmelt that is within about 400° C. of the melt temperature Tmelt. The method also includes scanning at least one second laser beam over the patterned surface and relative to the first laser beam. The at least one second laser beam is pulsed and is configured to heat the patterned surface from the non-melt temperature provided by the at least one first laser beam up to the melt temperature.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: November 13, 2012
    Assignee: Ultratech, Inc.
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Patent number: 8299446
    Abstract: Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: October 30, 2012
    Assignee: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Emily True, Manish Ranjan, Warren Flack, Detlef Fuchs
  • Publication number: 20120223062
    Abstract: Apparatuses and methods are provided for processing a surface of a substrate. The substrate may have a surface pattern that exhibits directionally and/or orientationally different reflectivities relative to radiation of a selected wavelength and polarization. The apparatus may include a radiation source that emits a photonic beam of the selected wavelength and polarization directed toward the surface at orientation angle and incidence angle selected to substantially minimize substrate surface reflectivity variations and/or minimize the maximum substrate surface reflectivity during scanning. Also provided are methods and apparatuses for selecting an optimal orientation and/or incidence angle for processing a surface of a substrate.
    Type: Application
    Filed: May 15, 2012
    Publication date: September 6, 2012
    Applicant: Ultratech, Inc.
    Inventor: Andrew M. Hawryluk
  • Publication number: 20120153323
    Abstract: Photolithographic methods of forming a roughened surface for an LED to improve LED light emission efficiency are disclosed. The methods include photolithographically imaging a phase-shift mask pattern onto a photoresist layer of a substrate to form therein a periodic array of photoresist features. The roughened substrate surface is created by processing the exposed photoresist layer to form a periodic array of substrate posts in the substrate surface. A p-n junction multilayer structure is then formed atop the roughened substrate surface to form the LED. The periodic array of substrate posts serve as scatter sites that improve the LED light emission efficiency as compared to the LED having no roughened substrate surface. The use of the phase-shift mask enables the use of affordable photolithographic imaging at a depth of focus suitable for non-flat LED substrates while also providing the needed resolution to form the substrate posts.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Inventors: Andrew M. Hawryluk, Robert L. Hsieh, Warren W. Flack
  • Publication number: 20120111838
    Abstract: Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.
    Type: Application
    Filed: January 10, 2012
    Publication date: May 10, 2012
    Applicant: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk, James T. McWhirter, Serguei G. Anikitchev
  • Patent number: 8153930
    Abstract: Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate. The image may be scanned across the surface to heat at least a portion of the substrate surface to achieve a desired temperature within a predetermined dwell time. Such processing may achieve a high efficiency due to the large proportion of energy contained in the uniform portion of the beam.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: April 10, 2012
    Assignee: Ultratech, Inc.
    Inventors: Andrew M Hawryluk, Boris Grek, David A Markle
  • Publication number: 20120062726
    Abstract: An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength ?LED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness ?S. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. An image sensor detects the superimposed image. An image processing unit processes the detected superimposed image to measure an alignment offset between the wafer and the reticle.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 15, 2012
    Inventors: Robert L. Hsieh, Khiem Nguyen, Warren W. Flack, Andrew M. Hawryluk
  • Patent number: 8088633
    Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: January 3, 2012
    Assignee: Ultratech, Inc.
    Inventors: Robert L. Hsieh, Khiem Nguyen, Warren W. Flack, Andrew M. Hawryluk
  • Publication number: 20110309374
    Abstract: Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing having a time duration of 10 seconds or faster. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.
    Type: Application
    Filed: August 24, 2011
    Publication date: December 22, 2011
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Publication number: 20110298093
    Abstract: Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.
    Type: Application
    Filed: August 15, 2011
    Publication date: December 8, 2011
    Applicant: ULTRATECH, INC.
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk, James T. McWhirter, Serguei G. Anikitchev
  • Patent number: 8067305
    Abstract: Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: November 29, 2011
    Assignee: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk
  • Publication number: 20110278587
    Abstract: Methods of performing fast thermal annealing in forming GaN light-emitting diodes (LEDs) are disclosed, as are GaN LEDs formed using fast thermal annealing. An exemplary method includes forming a GaN multilayer structure having a n-GaN layer and a p-GaN layer that sandwich an active layer. The method includes performing fast thermal annealing of the p-GaN layer using either a laser or a flash lamp. The method further includes forming a transparent conducting layer atop the GaN multilayer structure, and adding a p-contact to the transparent conducting layer and a n-contact to the n-GaN layer. The resultant GaN LEDs have enhanced output power, lower turn-on voltage and reduced series resistance.
    Type: Application
    Filed: July 20, 2011
    Publication date: November 17, 2011
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Patent number: 7960993
    Abstract: Each sensor of a linear array of sensors includes, in part, a sensing electrode and an associated feedback circuit. The sensing electrodes are adapted to be brought in proximity to a flat panel having formed thereon a multitude of pixel electrodes in order to capacitively measure the voltage of the pixel electrodes. Each feedback circuit is adapted to actively drive its associated electrode via a feedback signal so as to maintain the voltage of its associated electrode at a substantially fixed bias. Each feedback circuit may include an amplifier having a first input terminal coupled to the sensing electrode and a second input terminal coupled to receive a biasing voltage. The output signal of the amplification circuit is used to generate the feedback signal that actively drives the sensing electrode. The biasing voltage may be the ground potential.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: June 14, 2011
    Assignee: Photon Dynamics, Inc.
    Inventors: David W. Gardner, Andrew M. Hawryluk