Abstract: A mounting assembly is usable with a vehicle device, such as a steering wheel of a vehicle, and a camera assembly. The mounting assembly is configured to hold a camera assembly in a desired position relative to the vehicle device. The mounting assembly comprises an elongated member having a clamping system configured to affix to the vehicle device, an adjustable arm assembly connected to the elongated member, and a camera connection device connected to the adjustable arm and having a mount for receiving the camera assembly.

Abstract: Methods of producing recombinant, multi-component proteins in eukaryotic expression systems, comprising co-transforming a eukaryotic cell with two or more different nucleic acid constructs, each comprising a respective transcriptional unit encoding a protein component, wherein each nucleic acid construct comprises the same promoter and signal sequence, such that each of the components will be targeted to the same organelle of the cell for expression and intracellular assembly. In one or more embodiments, each nucleic acid construct comprises a promoter from a protein storage gene that is operably linked to a DNA sequence that encodes for a protein storage-specific signal sequence.

Abstract: The subject method for delivering power to a moving target wirelessly via electromagnetic time reversal can find applications in wireless electrical transmission to portable devices, wireless heating of portable devices, novel wirelessly powered accelerometers, hyperthermic treatment of cancers, and many other applications. The subject non-linear time reversed electromagnetic waves based wireless power transmission (WPT) system targets either a single linear or non-linear object where a selective targeting between two diodes has been demonstrated simultaneously with different degrees of non-linearity in a three-dimensional ray-chaotic billiard model. A dual-purpose rectenna with harmonic generation for wireless power transfer by non-linear time-reversal has been designed for the subject system using the Schottky diode.

Abstract: The subject method for delivering power to a moving target wirelessly via electromagnetic time reversal can find applications in wireless electrical transmission to portable devices, wireless heating of portable devices, novel wirelessly powered accelerometers, hyperthermic treatment of cancers, and many other applications. The subject non-linear time reversed electromagnetic waves based wireless power transmission (WPT) system targets either a single linear or non-linear object where a selective targeting between two diodes has been demonstrated simultaneously with different degrees of non-linearity in a three-dimensional ray-chaotic billiard model. A dual-purpose rectenna with harmonic generation for wireless power transfer by non-linear time-reversal has been designed for the subject system using the Schottky diode.

Abstract: Various moisture retention seals are disclosed, in the contexts of canisters and corresponding closures forming packages for avoiding moisture evaporation and in retaining liquid or moisture contained in the packages.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: A trench is opened in a dielectric layer. The trench is then lined with a sandwiched diffusion barrier and metal liner structure and a metal seed layer. The sandwiched diffusion barrier and metal liner structure includes a conformal metal liner layer sandwiched between a first diffusion barrier layer and a second diffusion barrier layer. The metal seed layer is at least lightly doped. The lined trench is then filled by electroplating with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.

Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.

Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: A strip dispenser (70) for dispensing one strip (S) from a plurality of strips (S). The strip dispenser (70) includes a container (2) that is constructed and arranged to hold a number of strips (S). There is a first structure (3) that defines one or more thin slots (8) that are generally parallel to the perimeter of the container (2), and that have a smallest dimension that is greater than the smallest dimension of a strip (S), where the slots (8) are configured and arranged to inhibit two strips that are stuck together back to back from passing through the slot (8) together. There is also a strip sorting structure (4) that inhibits a strip (S) that has at least partially passed through a slot (8) from fully leaving the container (2) until the strip (S) is pulled out of the container (2) by the user.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: A dispensing apparatus includes a container having an opening, and a doser coupled with the container about the container opening. The doser includes a housing forming a chamber with an interior wall, an inlet, and an outlet. The inlet is diametrically offset from the outlet, and substantially aligned with the opening of the container. The doser also includes a covering member to alternatively cover and open the inlet and the outlet. The covering member is movable about a range of positions to substantially completely cover at least one of the inlet and outlet at all positions in the range. The covering member covers no more than a portion of the chamber interior wall when the covering member completely opens the outlet.

Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.