Abstract: A system and method for a virtual processor base/virtual execution context arrangement. The disclosed arrangement utilizes chiplets comprising core logic and defined instruction sets. The chiplets are adapted to operate in conjunction with one or more active execution contexts to enable the execution of particular processes. In particular, the defined instruction sets includes a instructions for processor debugging. The system and method support the compartmentalization of such debugging instructions so as to provide enhanced processor and process security.

Abstract: A system and method for the storage within one or more virtual execution context registers private code representative of processes or other information requiring an enhanced degree of security. The storage of the private code can be performed as a function of the type of code or in response to one or more markers embedded within the code. The time-variant nature of the virtual execution context registers affords a high degree of inherent security for the private code data stored within.

Abstract: Methods and systems for mapping a sharable resource using a one-time password are disclosed. An identifier included in a set of provided credentials uniquely associates the one-time password with an executable within a computing environment that hosts the sharable resource. When credentials are received in association with a mapping request, it is determined whether a supplied username corresponds to a user authorized to access the sharable resource and whether a representation of a supplied password received in association with the mapping request matches a representation of the one-time password. Validating the mapping request provides access to the sharable resource.

Abstract: A proxy compiler may be used within a native execution environment to enable execution of non-native instructions from a non-native execution environment as if being performed within the native execution environment. In particular, the proxy compiler coordinates creation of a native executable that is uniquely tied to a particular non-native image at the time of creation of the non-native image. This allows a trusted relationship between the native executable and the non-native image, while avoiding a requirement of compilation/translation of the non-native instructions for execution directly within the native execution environment.

Abstract: A system and method for a virtual processor base/virtual execution context arrangement. The disclosed arrangement utilizes chiplets comprising core logic and defined instruction sets. The chiplets are adapted to operate in conjunction with one or more active execution contexts to enable the execution of particular processes. In particular, the defined instruction sets includes a instructions for processor debugging. The system and method support the compartmentalization of such debugging instructions so as to provide enhanced processor and process security.

Abstract: A system and method for the provision of a shared register within a virtual processor base/virtual execution context arrangement. The disclosed arrangement utilizes chiplets comprising core logic and defined instruction sets. The chiplets are adapted to operate in conjunction with one or more active execution contexts to enable the execution of particular processes. In particular, the shared register space is created within the same physical memory utilized to supports execution contexts.

Abstract: A system and method for the storage, within one or more virtual execution context registers, execution tracing information indicative of process/code flow within a processor system. This stored information can include a time stamp, information indicative of where the instruction pointer of the system was pointing prior to any process discontinuity, information indicative of where the instruction pointer of the system was pointing after any process discontinuity, and the number of times a specific instruction or sub-process is executed during a particular process. The data collected and stored can be utilized within such a system for the identification and analysis of code interrupts and profile-guided optimization.

Abstract: A system and method for virtual processor customization based upon the particular workload placed upon the virtual processor by one or more execution contexts within a given program or process. The customization serves to optimize the virtual processor architecture based upon a determination as to the size and/or type or virtual execution registers optimally suited for supporting a given execution context. This results in a time-variant processor architecture comprised of a virtual processor base and a virtual execution context.

Abstract: A system and method for virtual processor customization based upon the particular workload placed upon the virtual processor by one or more execution contexts within a given program or process. The customization serves to optimize the virtual processor architecture based upon a determination as to the size and/or type or virtual execution registers optimally suited for supporting a given execution context. This results in a time-variant processor architecture which not only provides optimized computational attributes, but also affords a high degree of inherent process security.

Abstract: A system and method for the storage within one or more virtual execution context registers private code representative of processes or other information requiring an enhanced degree of security. The storage of the private code can be performed as a function of the type of code or in response to one or more markers embedded within the code. The time-variant nature of the virtual execution context registers affords a high degree of inherent security for the private code data stored within.

Abstract: A system and method for the storage, within one or more virtual execution context registers, tracing information indicative of process/code flow within a processor system. This stored information can include a time stamp, information indicative of where the instruction pointer of the system was pointing prior to any process discontinuity, information indicative of where the instruction pointer of the system was pointing after any process discontinuity, and the number of times a specific instruction or sub-process is executed during a particular process. The data collected and stored can be utilized within such a system for the identification and analysis of processing hot-spots.

Abstract: A proxy compiler may be used within a native execution environment to enable execution of non-native instructions from a non-native execution environment as if being performed within the native execution environment. In particular, the proxy compiler coordinates creation of a native executable that is uniquely tied to a particular non-native image at the time of creation of the non-native image. This allows a trusted relationship between the native executable and the non-native image, while avoiding a requirement of compilation/translation of the non-native instructions for execution directly within the native execution environment.

Abstract: Methods and systems for implementing independent time in a hosted operating environment are disclosed. The hosted, or guest, operating environment, can be seeded with a guest time value by a guest operating environment manager that maintains a time delta between a host clock time and an enterprise time. The guest operating environment can subsequently manage its guest clock from the guest time value. If the guest operating environment is halted, the guest operating environment manager can manage correspondence between the host clock time and the enterprise time by periodically assessing divergence between actual and expected values of the host clock time.

Abstract: Systems and methods for executing compiled code having parallel code fragments is provided. One method includes storing executable code having a plurality of parallel code fragments, each of the plurality of parallel code fragments representing alternative executable paths through a code stream. The method further includes determining a code level supported by a processor executable at a computing system, the processor executable supporting a hosted computing environment. The method also includes translating the executable code into machine-readable code executable by a processor of the computing system. Translating the executable code includes selecting a code fragment from among the plurality of parallel code fragments for execution based on the code level supported by the processor executable. The method includes executing the machine-readable code within the hosted computing environment.

Abstract: A proxy compiler may be used within a native execution environment to enable execution of non-native instructions from a non-native execution environment as if being performed within the native execution environment. In particular, the proxy compiler coordinates creation of a native executable that is uniquely tied to a particular non-native image at the creation time of the non-native image. This allows a trusted relationship between the native executable and the non-native image, while avoiding a requirement of compilation/translation of the non-native instructions for execution directly within the native execution environment.

Abstract: Methods and systems described herein utilize a jump table in directly-addressable, near code, to facilitate improved execution of frequent calls to executable code from other workloads outside of the near code. By executing a directly-addressable call and jump instruction to access frequently-accessed executable code, indirect call instructions are avoided.

Abstract: A system and method for the dynamic, run-time configuration of logic core register files, and the provision of an associated execution context. The dynamic register files as well as the associated execution context information are software-defined so as to be virtually configured in random-access memory. This virtualization of both the processor execution context and register files enables the size, structure and performance to be specified at run-time and tailored to the specific processing, instructions and data associated with a given processor state or thread, thereby minimizing both the aggregate memory required and the context switching time. In addition, the disclosed system and method provides for processor virtualization which further enhances the flexibility and efficiency.

Abstract: A system and method for the dynamic, run-time configuration of logic core register files, and the provision of an associated execution context. The dynamic register tiles as well as the associated execution context information are software-defined so as to be virtually configured in random-access memory. This virtualization of both the processor execution context and register files enables the size, structure and performance to be specified at run-time and tailored to the specific processing, instructions and data associated with a given processor state or thread, thereby minimizing both the aggregate memory required and the context switching time. In addition, the disclosed system and method provides for processor virtualization which further enhances the flexibility and efficiency.

Abstract: A system and method for the dynamic, run-time configuration of logic core register files, and the provision of an associated execution context. The dynamic register files as well as the associated execution context information are software-defined so as to be virtually configured in random-access memory. This virtualization of both the processor execution context and register files enables the size, structure and performance to be specified at run-time and tailored to the specific processing, instructions and data associated with a given processor state or thread, thereby minimizing both the aggregate memory required and the context switching time. In addition, the disclosed system and method provides for processor virtualization which further enhances the flexibility and efficiency.

Abstract: A system and method for the dynamic, run-time configuration of logic core register files, and the provision of an associated execution context. The dynamic register files as well as the associated execution context information are software-defined so as to be virtually configured in random-access memory. This virtualization of both the processor execution context and register files enables the size, structure and performance to be specified at run-time and tailored to the specific processing, instructions and data associated with a given processor state or thread, thereby minimizing both the aggregate memory required and the context switching time. In addition, the disclosed system and method provides for processor virtualization which further enhances the flexibility and efficiency.