Patents by Inventor Andrew Ward Beale

Andrew Ward Beale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110016458
    Abstract: Various embodiments of systems and methods for dynamic binary translation in an interpreter are disclosed. An embodiment comprises a method for dynamic binary translation in an interpreter.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Inventors: Andrew Ward Beale, Robert Joseph Meyers, Loren C. Wilton
  • Patent number: 7415632
    Abstract: An embodiment of the invention is a technique to detect data corruption of critical data structures and to repair the corrupted critical data structures. Information data of critical data structures used by a managing module are captured upon initialization of the managing module. The captured information data are considered valid, and stored in a data vault. Critical data structures used by the managing module are monitored for validity during operation of the managing module. A corruption of a critical data structure corresponding to a stored data of the stored captured information data is detected during operation of the managing module. The corrupted data structure is restored to an operational state by using the corresponding stored data in the data vault without interrupting the operation of the managing module.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: August 19, 2008
    Assignee: Unisys Corporation
    Inventors: Andrew Ward Beale, Jason Alan Yelinek
  • Patent number: 6738847
    Abstract: A method is disclosed for use in a multi-processor computer system having a multiplicity of peripherals coupled thereto. The disclosed method assigns interrupt vectors from the multiplicity of peripherals, and includes the steps of determining if an interrupt resource from a given peripheral has already been assigned, and if not; assigning an affinity and vector to this interrupt resource. Moreover, a determination is made if the affinity and vector assigned in the previous step are within the operational characteristics of the multi-processor computer system.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: May 18, 2004
    Assignee: Unisys Corporation
    Inventors: Andrew Ward Beale, Derek William Paul
  • Patent number: 6128679
    Abstract: A computer for executing I/O instructions, by emulation, in a foreign application program includes an emulator program which has a Send thread, a Get thread, and single Result thread. The Send thread calls into a native operating system for the computer to send data from the foreign application program to an I/O port. The Get thread calls into the native operating system to receive data from the I/O port for the foreign application program. The Result thread processes one result descriptor from the native operating system when data is sent for the Send thread, and processes another result descriptor from the native operating system when data is received for the Get thread, and is completely blocked from running on the computer between the processing of the result descriptors.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: October 3, 2000
    Assignee: Unisys Corporation
    Inventors: Andrew Ward Beale, Bong Jae Lee, Dwayne Eugene Ebersole