Patents by Inventor Andy Wei

Andy Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10262941
    Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Jason Eugene Stephens, Tuhin Guha Neogi, Kai Sun, Deniz Elizabeth Civay, David Charles Pritchard, Andy Wei
  • Patent number: 10181420
    Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jason Eugene Stephens, David Michael Permana, Guillaume Bouche, Andy Wei, Mark Zaleski, Anbu Selvam K M Mahalingam, Craig Michael Child, Jr., Roderick Alan Augur, Shyam Pal, Linus Jang, Xiang Hu, Akshey Sehgal
  • Patent number: 10056458
    Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chang Ho Maeng, Andy Wei, Anthony Ozzello, Bharat Krishnan, Guillaume Bouche, Haifeng Sheng, Haigou Huang, Huang Liu, Huy M. Cao, Ja-Hyung Han, SangWoo Lim, Kenneth A. Bates, Shyam Pal, Xintuo Dai, Jinping Liu
  • Publication number: 20180226294
    Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jason Eugene STEPHENS, David Michael PERMANA, Guillaume BOUCHE, Andy WEI, Mark ZALESKI, Anbu Selvam KM MAHALINGAM, Craig Michael CHILD, JR., Roderick Alan AUGUR, Shyam PAL, Linus JANG, Xiang HU, Akshey SEHGAL
  • Patent number: 9852984
    Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Wei, Sudharshanan Raghunathan
  • Publication number: 20170309560
    Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 26, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume BOUCHE, Jason Eugene STEPHENS, Tuhin GUHA NEOGI, Kai SUN, Deniz Elizabeth CIVAY, David Charles PRITCHARD, Andy WEI
  • Publication number: 20170200792
    Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Inventors: Chang Ho MAENG, Andy WEI, Anthony OZZELLO, Bharat KRISHNAN, Guillaume BOUCHE, Haifeng SHENG, Haigou HUANG, Huang LIU, Huy M. CAO, Ja-Hyung HAN, SangWoo LIM, Kenneth A. BATES, Shyam PAL, Xintuo DAI, Jinping LIU
  • Patent number: 9659928
    Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 23, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Roman Boschke, Markus Forsberg
  • Patent number: 9620587
    Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan
  • Patent number: 9601486
    Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Anil Kumar
  • Patent number: 9583351
    Abstract: An inverted contact and methods of fabrication are provided. A sacrificial layer is patterned in an inverted trapezoid shape, and oxide is deposited around the pattern. The sacrificial layer is removed, and a metal contact material is deposited, taking an inverted-trapezoid shape. Embodiments of the present invention provide an inverted contact, having a wider base and a narrower top. The wider base provides improved electrical contact to the underlying active area. The narrower top allows for closer placement of adjacent contacts, serving to increase overall circuit density of an integrated circuit.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Andy Wei
  • Patent number: 9520395
    Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan
  • Patent number: 9508850
    Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhenyu Hu, Richard J. Carter, Andy Wei, Qi Zhang, Sruthi Muralidharan, Amy L. Child
  • Publication number: 20160329278
    Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.
    Type: Application
    Filed: April 21, 2016
    Publication date: November 10, 2016
    Inventors: Guillaume BOUCHE, Andy WEI, Sudharshanan RAGHUNATHAN
  • Publication number: 20160322298
    Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Guillaume BOUCHE, Andy WEI, Sudharshanan RAGHUNATHAN
  • Patent number: 9455316
    Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan
  • Patent number: 9450073
    Abstract: By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Roman Boschke, Casey Scott
  • Patent number: 9449826
    Abstract: In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: G Robert Mulfinger, Andy Wei, Jan Hoentschel, Vassilios Papageorgiou
  • Publication number: 20160260701
    Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jagar SINGH, Andy WEI, Mahadeva Iyer NATARAJAN, Manjunatha PRABHU, Anil KUMAR
  • Patent number: 9437713
    Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Andy Wei, Gopal Srinivasan, Amaury Gendron