Patents by Inventor Andy Wei
Andy Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9224638Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.Type: GrantFiled: May 12, 2014Date of Patent: December 29, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Hiroaki Niimi, Kisik Choi, Hoon Kim, Andy Wei, Guillaume Bouche
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Patent number: 9219002Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.Type: GrantFiled: September 17, 2013Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Zhenyu Hu, Andy Wei, Qi Zhang, Richard J. Carter, Hongliang Shen, Daniel Pham, Sruthi Muralidharan
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Patent number: 9196694Abstract: Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.Type: GrantFiled: October 1, 2013Date of Patent: November 24, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Guillaume Bouche, Shao Ming Koh, Jeremy A. Wahl, Andy Wei
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Patent number: 9196710Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.Type: GrantFiled: February 11, 2014Date of Patent: November 24, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Andy Wei, Jin Ping Liu, Shao Ming Koh, Amaury Gendron
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Publication number: 20150333067Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: ApplicationFiled: July 29, 2015Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
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Publication number: 20150325473Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.Type: ApplicationFiled: May 12, 2014Publication date: November 12, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Hiroaki NIIMI, Kisik CHOI, Hoon KIM, Andy WEI, Guillaume BOUCHE
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Patent number: 9184095Abstract: In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches.Type: GrantFiled: November 2, 2010Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel, Andy Wei
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Patent number: 9177951Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.Type: GrantFiled: January 6, 2014Date of Patent: November 3, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Jagar Singh, Andy Wei, Mahadeva Iyer Natarajan
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Publication number: 20150287595Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.Type: ApplicationFiled: May 29, 2015Publication date: October 8, 2015Inventors: Andy WEI, Mariappan HARIHARAPUTHIRAN, Dae Geun YANG, Dae-Han CHOI, Xiang HU, Richard J. CARTER, Akshey SEHGAL
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Patent number: 9147696Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: GrantFiled: October 1, 2013Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Jing Wan, Andy Wei, Lun Zhao, Dae Geun Yang, Jin Ping Liu, Tien-Ying Luo, Guillaume Bouche, Mariappan Hariharaputhiran, Churamani Gaire
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Publication number: 20150263089Abstract: A non-planar diode is fabricated, with an n- or p-type raised structure, such as a fin, coupled to the substrate. A well of an opposite type is located under the raised structure, along with an area having additional impurity, located directly under the raised structure, and within the well. This additional implant creates a p-n junction within the substrate, the non-planar diode having an ideality factor in a range of 1 to about 1.05.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Inventors: Jagar SINGH, Andy WEI
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Patent number: 9136175Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.Type: GrantFiled: September 16, 2013Date of Patent: September 15, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Andy Wei, Peter Baars, Erik P. Geiss
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Publication number: 20150255353Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.Type: ApplicationFiled: March 5, 2014Publication date: September 10, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing WAN, Andy WEI, Jinping LIU, Xiang HU, Dae-han CHOI, Dae Geun YANG, Churamani GAIRE, Akshey SEHGAL
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Patent number: 9129987Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.Type: GrantFiled: January 24, 2014Date of Patent: September 8, 2015Assignee: GLOBAL FOUNDRIES, Inc.Inventors: Jing Wan, Jin Ping Liu, Guillaume Bouche, Andy Wei, Lakshmanan H. Vanamurthy, Cuiqin Xu, Sridhar Kuchibhatla, Rama Kambhampati, Xiuyu Cai
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Patent number: 9123568Abstract: A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.Type: GrantFiled: November 21, 2013Date of Patent: September 1, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Peter Baars, Richard Carter, Andy Wei
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Publication number: 20150236133Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Inventors: Jagar SINGH, Andy WEI, Gopal SRINIVASAN, Amaury GENDRON
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Publication number: 20150228755Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.Type: ApplicationFiled: February 11, 2014Publication date: August 13, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Andy Wei, Jin Ping Liu, Shao Ming Koh, Amaury Gendron
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Publication number: 20150228649Abstract: A fin of a FinFET, being p or n-type, includes a well encompassing the active region, the well being of the opposite type than the fin. An implant of the same type as the well is provided for the well tap at an edge of the active region. A dummy gate material on the fin between the source/drain and the well tap implant reduces an inherent resistance of a well tap contact.Type: ApplicationFiled: February 10, 2014Publication date: August 13, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jagar Singh, Andy Wei
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Patent number: 9105478Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.Type: GrantFiled: October 28, 2013Date of Patent: August 11, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Andy Wei, Mariappan Hariharaputhiran, Dae Geun Yang, Dae-Han Choi, Xiang Hu, Richard J. Carter, Akshey Sehgal
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Publication number: 20150214330Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing WAN, Jin Ping LIU, Guillaume BOUCHE, Andy WEI, Lakshmanan H. VANAMURTHY, Cuiqin XU, Sridhar KUCHIBHATLA, Rama KAMBHAMPATI, Xiuyu CAI