Patents by Inventor Andy Wei

Andy Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same
    Patent number: 7829421
    Abstract: By forming a portion of a PN junction within strained silicon/germanium material in SOI transistors with a floating body architecture, the junction leakage may be significantly increased, thereby reducing floating body effects. The positioning of a portion of the PN junction within the strained silicon/germanium material may be accomplished on the basis of implantation and anneal techniques, contrary to conventional approaches in which in situ doped silicon/germanium is epitaxially grown so as to form the deep drain and source regions. Consequently, high drive current capability may be combined with a reduction of floating body effects.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 9, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG A CRYSTALLOGRAPHIC ORIENTATION WITH INCREASED CHARGE CARRIER MOBILITY
    Publication number: 20100252866
    Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
    Type: Application
    Filed: June 23, 2010
    Publication date: October 7, 2010
    Inventors: Igor Peidous, Thorsten Kammler, Andy Wei
  • Method for creating tensile strain by repeatedly applied stress memorization techniques
    Patent number: 7790537
    Abstract: By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: September 7, 2010
    Assignee: Globalfoundries Inc.
    Inventors: Andy Wei, Anthony Mowry, Andreas Gehring, Maciej Wiatr
  • Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region
    Patent number: 7772077
    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: August 10, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andreas Gehring, Andy Wei, Anthony Mowry, Manuj Rathor
  • SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION
    Publication number: 20100193860
    Abstract: In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.
    Type: Application
    Filed: January 25, 2010
    Publication date: August 5, 2010
    Inventors: Thilo Scheiper, Andy Wei, Sven Beyer
  • GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES
    Publication number: 20100193866
    Abstract: In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.
    Type: Application
    Filed: January 25, 2010
    Publication date: August 5, 2010
    Inventors: G Robert Mulfinger, Andy Wei, Jan Hoentschel, Vassilios Papageorgiou
  • Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility
    Patent number: 7767540
    Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: August 3, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Igor Peidous, Thorsten Kammler, Andy Wei
  • TENSILE STRAIN SOURCE USING SILICON/GERMANIUM IN GLOBALLY STRAINED SILICON
    Publication number: 20100187629
    Abstract: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.
    Type: Application
    Filed: April 5, 2010
    Publication date: July 29, 2010
    Inventors: Andy Wei, Karla Romero, Manfred Horstmann
  • Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate
    Patent number: 7763515
    Abstract: By combining a respectively adapted lattice mismatch between a first semiconductor material in a channel region and an embedded second semiconductor material in an source/drain region of a transistor, the strain transfer into the channel region is increased. According to one embodiment of the invention, the lattice mismatch may be adapted by a biaxial strain in the first semiconductor material. According to one embodiment, the lattice mismatch may be adjusted by a biaxial strain in the first semiconductor material. In particular, the strain transfer of strain sources including the embedded second semiconductor material as well as a strained overlayer is increased. According to one illustrative embodiment, regions of different biaxial strain may be provided for different transistor types.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: July 27, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy Wei, Thorsten Kammler, Roman Boschke, Manfred Horstmann
  • METHOD OF FORMING A FIELD EFFECT TRANSISTOR
    Publication number: 20100181619
    Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.
    Type: Application
    Filed: April 1, 2010
    Publication date: July 22, 2010
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS
    Publication number: 20100155727
    Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
    Type: Application
    Filed: March 3, 2010
    Publication date: June 24, 2010
    Inventors: ANTHONY MOWRY, Casey Scott, Vassilios Papageorgiou, Andy Wei, Markus Lenski, Andreas Gehring
  • TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS
    Publication number: 20100155850
    Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.
    Type: Application
    Filed: February 23, 2010
    Publication date: June 24, 2010
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann, Peter Javorka, Joe Bloomquist
  • MULTIPLE GATE TRANSISTOR HAVING FINS WITH A LENGTH DEFINED BY THE GATE ELECTRODE
    Publication number: 20100133615
    Abstract: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.
    Type: Application
    Filed: November 17, 2009
    Publication date: June 3, 2010
    Inventors: Robert Mulfinger, Andy Wei, Jan Hoentschel, Andrew Waite
  • Method of forming a field effect transistor
    Patent number: 7723195
    Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: May 25, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor
    Patent number: 7723174
    Abstract: The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: May 25, 2010
    Assignee: Globalfoundries Inc.
    Inventors: Andrew Waite, Andy Wei, Gunter Grasshoff
  • Tensile strain source using silicon/germanium in globally strained silicon
    Patent number: 7719060
    Abstract: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 18, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Karla Romero, Manfred Horstmann
  • Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
    Patent number: 7713763
    Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: May 11, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Mowry, Casey Scott, Vassilios Papageorgiou, Andy Wei, Markus Lenski, Andreas Gehring
  • RECESSED DRAIN AND SOURCE AREAS IN COMBINATION WITH ADVANCED SILICIDE FORMATION IN TRANSISTORS
    Publication number: 20100109091
    Abstract: During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency.
    Type: Application
    Filed: August 28, 2009
    Publication date: May 6, 2010
    Inventors: Uwe Griebenow, Andy Wei, Jan Hoentschel, Thilo Scheiper
  • HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS
    Publication number: 20100090321
    Abstract: By providing a high-k dielectric etch stop material as an etch stop layer for patterning an interlayer dielectric material, enhanced performance and higher flexibility may be achieved since, for instance, an increased amount of highly stressed dielectric material may be positioned more closely to the respective transistors due to the reduced thickness of the high-k dielectric etch stop material.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 15, 2010
    Inventors: Robert Mulfinger, Andy Wei, Roman Boschke, Casey Scott
  • Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions
    Patent number: 7696052
    Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: April 13, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann, Peter Javorka, Joe Bloomquist