Abstract: A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced efficiency for the strain generation.

Abstract: In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.

Abstract: By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.

Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

Abstract: A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.

Abstract: By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.

Abstract: By performing multiple radiation-based anneal processes on the basis of less critical process parameters, the overall risk for creating anneal-induced damage, such as melting of gate portions, may be substantially avoided while nevertheless the respective degree of dopant activation may be enhanced for each individual anneal process. Consequently, the sheet resistance of advanced transistor devices may be reduced with a decreasing number of sequential anneal processes.

Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Abstract: By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

Abstract: By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

Abstract: A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover.

Abstract: By combining a respectively adapted lattice mismatch between a first semiconductor material in a channel region and an embedded second semiconductor material in an source/drain region of a transistor, the strain transfer into the channel region is increased. According to one embodiment of the invention, the lattice mismatch may be adapted by a biaxial strain in the first semiconductor material. According to one embodiment, the lattice mismatch may be adjusted by a biaxial strain in the first semiconductor material. In particular, the strain transfer of strain sources including the embedded second semiconductor material as well as a strained overlayer is increased. According to one illustrative embodiment, regions of different biaxial strain may be provided for different transistor types.

Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Abstract: By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.

Abstract: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract: By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.

Abstract: By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

Abstract: By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, the formation of individually positioned semiconductor materials in different transistors may be accomplished on the basis of a differential disposable spacer approach, thereby combining high efficiency with low process complexity even for highly advanced SOI transistor devices.