Patents by Inventor Angela Hui
Angela Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8022468Abstract: A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.Type: GrantFiled: March 29, 2005Date of Patent: September 20, 2011Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Wenmei Li, Jeffrey A. Shields, Ning Cheng, Angela Hui, Cinti Xiaohua Chen
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Patent number: 8012830Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: GrantFiled: August 8, 2007Date of Patent: September 6, 2011Assignee: Spansion LLCInventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Patent number: 7951675Abstract: Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.Type: GrantFiled: December 17, 2007Date of Patent: May 31, 2011Assignee: Spansion LLCInventors: Lei Xue, Aimin Xing, Chih-Yuh Yang, Angela Hui, Chungho Lee
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Patent number: 7906807Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: GrantFiled: June 30, 2010Date of Patent: March 15, 2011Assignee: Spansion LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, Kuo-Tung Chang, Huaqiang Wu
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Publication number: 20100264480Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: SPANSION LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, K.T Chang, Huaqiang Wu
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Publication number: 20100230743Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: ApplicationFiled: May 26, 2010Publication date: September 16, 2010Inventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
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Patent number: 7785965Abstract: Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.Type: GrantFiled: September 8, 2006Date of Patent: August 31, 2010Assignee: Spansion LLCInventors: Unsoon Kim, Kyunghoon Min, Ning Cheng, Hiroyuki Kinoshita, Sugino Rinji, Timothy Thurgate, Angela Hui, Jihwan Choi, Chi Chang
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Patent number: 7776688Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: GrantFiled: August 8, 2007Date of Patent: August 17, 2010Assignee: Spansion LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, Kuo-Tung Chang, Huaqiang Wu
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Publication number: 20100155817Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Applicant: SPANSION LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
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Patent number: 7732276Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: GrantFiled: April 26, 2007Date of Patent: June 8, 2010Assignee: Spansion LLCInventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
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Publication number: 20100133646Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.Type: ApplicationFiled: February 3, 2010Publication date: June 3, 2010Inventors: Shenqing FANG, Angela HUI, Shao-Yu TING, Inkuk KANG, Gang XUE
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Publication number: 20100099249Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: ApplicationFiled: December 22, 2009Publication date: April 22, 2010Applicant: SPANSION LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
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Patent number: 7696038Abstract: Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.Type: GrantFiled: April 26, 2006Date of Patent: April 13, 2010Assignee: Spansion LLCInventors: Ning Cheng, Kuo-Tung Chang, Hiroyuki Kinoshita, Timothy Thurgate, Wei Zheng, Ashot Melik-Martirosian, Angela Hui, Chih-Yuh Yang
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Patent number: 7691751Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: GrantFiled: October 26, 2007Date of Patent: April 6, 2010Assignee: Spansion LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
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Patent number: 7622389Abstract: A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.Type: GrantFiled: April 25, 2006Date of Patent: November 24, 2009Assignee: Spansion LLCInventors: Kyunghoon Min, Mark Chang, Ning Cheng, Brian Osborn, Kevin Song, Fei Wang, Angela Hui, Hiroyuki Kinoshita, Kuo-Tung Chang
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Publication number: 20090152669Abstract: Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.Type: ApplicationFiled: December 17, 2007Publication date: June 18, 2009Applicant: SPANSION LLCInventors: Lei Xue, Aimin Xing, Chih-Yuh Yang, Angela Hui, Chungho Lee
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Publication number: 20090111265Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: Spansion LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
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Publication number: 20090042378Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Applicant: SPANSION LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, K.T. Chang, Huaqiang Wu
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Publication number: 20090039405Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Applicant: SPANSION LLCInventors: Ning Cheng, K.T. Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Publication number: 20080265301Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: ApplicationFiled: April 26, 2007Publication date: October 30, 2008Inventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillips Jones, Mark Chang, Minh-Van Ngo