Abstract: A method and system for providing a contact hole between structures for a semiconductor device is disclosed. The method and system comprises etching a resist material on the semiconductor device to expose a surface of the structures; providing an implant to the surface of the structures; and removing the resist material from a gap between the structures. The method and system includes annealing the semiconductor device to cause the implant to adhere to the treated surface; and providing dielectric material within the gap. Finally, the method and system includes etching the contact hole in the gap between the structures. The contact hole can then be etched without damaging the structures. Accordingly, by providing an implant treated surface and then providing an anneal process the implant is bonded to the appropriate portion of the semiconductor structure.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

Abstract: The density of a deposited silicon nitride layer is increased by laser thermal annealing in N2, thereby increasing etch selectivity with respect to an overlying oxide and, hence, avoiding damage to underlying silicide layers and gates. Embodiments include laser thermal annealing a silicon nitride layer deposited as an etch stop layer, e.g., in fabricating EEPROMs, to increase its density by up to about 8%, thereby increasing its etch selectivity with respect to an overlying BPSG layer to about {fraction (1/12)} to about {fraction (1/14)}.

Abstract: The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

Abstract: A method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer.

Abstract: Methods are described for fabricating semiconductor devices, in which a tensile film is formed over PMOS transistors to cause a compressive stress therein and a compressive film is formed over NMOS transistors to achieve a tensile stress therein, by which improved carrier mobility is facilitated in both PMOS and NMOS devices.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

Abstract: A method for removing a hard mask during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material. The method includes a two-step removal process that includes performing a major wet etch to remove a majority of the hard mask material, followed by performing a minor dry etch that removes a remainder of the hard mask material.

Abstract: STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings.

Abstract: A method to improve LDD corner control during a local interconnect trench oxide etch on a semiconductor device by providing a first etch stop layer over the gate and active regions in the substrate and further providing thereon a second etch stop layer made of polysilicon and having of a different composition than that of the first etch stop layer. By forming a second etch stop layer of polysilicon the present invention improves the selectivity of the local interconnect trench oxide etch, thereby improving the ability of the first and second etch stop layers to stop the etch process at the critical interfaces.

Abstract: One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

Abstract: A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer material layer during the formation of sidewall spacers on the sidewalls of a gate. The exposed portions of the gate sidewalls are then covered by silicide formed during a silicidation process. The formation of the suicide on the gate sidewalls prevents the sidewall spacers from being preferentially attacked during a local interconnect etch or contact etch.

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

Abstract: A method of fabricating an integrated circuit including multiple devices and isolation structures separating the multiple devices includes depositing a mask layer with a first thickness above a semiconductor substrate, forming an aperture in the mask, and trimming the mask layer to a second thickness where the second thickness is less than the first thickness.

Abstract: A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased hardness in comparison to conventional etch stop layers, such as plasma enhanced chemical vapor deposition (PECVD) SiON etch stop layers. A PECVD process is used to deposit silicon carbide (SiC). The increased hardness of the SiC etch stop layer is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

Abstract: A method for rapid anisotropic dry etching of oxide compounds in high aspect ratio openings which etching method is highly selective to metal salicides and which method employs plasma gases of CHF.sub.3, N.sub.2 and a high flow rate of He at a high pressure and products made by the process.