Abstract: A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell.

Abstract: A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.

Abstract: Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.

Abstract: A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second selection transistor coupled between the memory cell and the first selection transistor, wherein the second selection transistor has a process defined threshold voltage.

Abstract: Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.

Abstract: The present invention relates to a process for the preparation of vegetable preserves, comprising immersing a vegetable in a solution containing darkening inhibitors, half cooking the vegetable in water at a temperate of between 90 and 100° C., immersing the vegetable in a brine solution containing probiotic lactobacilli and/or bifidobacteria in a sterile container and sealing the container. The invention further relates to vegetable and vegetable preserves obtained by means of the process.

Abstract: Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.

Abstract: A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second selection transistor coupled between the memory cell and the first selection transistor, wherein the second selection transistor has a process defined threshold voltage.

Abstract: A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution.

Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.

Abstract: An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

Abstract: A method is described for the total phosphine detection in cereal caryopses, comprising the steps of inserting a sample of cereal caryopses inside a container (1) equipped with hermetic closure (2); adding to the sample an aqueous solution of H2SO4 with a v/v concentration in the range of 5-20%, with obtainment of an aqueous dispersion, and hermetically closing the first container (1); subjecting the aqueous dispersion contained in the first container (1) to the action of microwaves for a time not greater than 3 minutes; drawing a predetermined volume of gas overlying the aqueous dispersion and detecting the phosphine possibly present by means of colorimetric and/or spectrophotometric methods, preferably by bringing it into contact with a predetermined volume of an aqueous solution of AgNO3 of known molarity, inside a second container (3) with hermetic closure and visually analysing the obtained color and/or spectrophotometrically measuring the absorbance at 400 nm of the aqueous solution.

Abstract: A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

Abstract: A memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal; a plurality of bit lines each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line; a plurality of first biasing lines each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line; a plurality of second biasing lines each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line; and means for programming at least one selected memory cell belonging to a selected row.

Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.

Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence. Each level representsmg a logic value consisting of a plurality of bits, wherein the structure includes components for detecting errors in the values of a selected block of memory cells. The structure further includes components for partitioning the bits of each memory cell of the block into a first subset and a second subset, the bits of the first subset being unchanged in the values of a first and a second ending range in the sequence. The components_for detecting errors only operate on the bits of the second subset of the block.

Abstract: A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.

Abstract: A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.