Abstract: An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

Abstract: A method is described for the total phosphine detection in cereal caryopses, comprising the steps of inserting a sample of cereal caryopses inside a container (1) equipped with hermetic closure (2); adding to the sample an aqueous solution of H2SO4 with a v/v concentration in the range of 5-20%, with obtainment of an aqueous dispersion, and hermetically closing the first container (1); subjecting the aqueous dispersion contained in the first container (1) to the action of microwaves for a time not greater than 3 minutes; drawing a predetermined volume of gas overlying the aqueous dispersion and detecting the phosphine possibly present by means of colorimetric and/or spectrophotometric methods, preferably by bringing it into contact with a predetermined volume of an aqueous solution of AgNO3 of known molarity, inside a second container (3) with hermetic closure and visually analysing the obtained colour and/or spectrophotometrically measuring the absorbance at 400 nm of the aqueous solution.

Abstract: A non-volatile memory device (100) is provided. Said memory device includes a matrix (105) of memory cells (110(i,j)) arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal; a plurality of bit lines (BLj) each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line; a plurality of first biasing lines (WLi) each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line; a plurality of second biasing lines (SLi) each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line; and means for programming (130b, 130s, 130w) at least one selected memory cell belonging to a selected row.

Abstract: The method for programming/erasing a non volatile memory cell device includes at least one electric stress step to apply, to at least one active oxide layer of at least one memory cell of the device, a stress electric field able to remove at least a part of charges trapped in the active oxide layer. The method may be used for devices with floating gate type memory cells. The electric stress step may include the application, to one or more terminals of at least one memory cell, of potentials able to produce an electric field on a corresponding active oxide layer.

Abstract: The invention relates to table olives enriched with probiotic microorganisms, in particular lactobacilli and bifidobacteria, food products containing them and a method for their preparation. The olives and food products of the invention provide an amount of microorganisms sufficient to exert a beneficial action on the gastro-intestinal tract and are particularly advantageous whenever administration of probotic food products of animal origin, in particular milk derivatives, is not possible.

Abstract: A method of programming a multi-level, electrically-programmable memory with memory cells electrically programmable into at least two distinct programmed states, includes: defining at least two programming sequences, each one being designed for bringing memory cells into at least one respective programmed state; receiving a pattern of data to be written into a selected group of memory cells of the memory; analyzing the pattern for determining sub-groups of memory cells, each sub-group of memory cells including the memory cells in the selected group that are to be brought into at least a respective one of the at least two programmed states; and submitting the memory cells in each sub-group to the respective programming sequence. A memory circuit and a computing system are also provided.

Abstract: A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.

Abstract: A method of programming a multi-level, electrically-programmable memory with memory cells electrically programmable into at least two distinct programmed states, includes: defining at least two programming sequences, each one being designed for bringing memory cells into at least one respective programmed state; receiving a pattern of data to be written into a selected group of memory cells of the memory; analysing the pattern for determining sub-groups of memory cells, each sub-group of memory cells including the memory cells in the selected group that are to be brought into at least a respective one of the at least two programmed states; and submitting the memory cells in each sub-group to the respective programming sequence. A memory circuit and a computing system are also provided.

Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.

Abstract: A method of re-programming an array of non-volatile memory cells after an erase operation is provided where a re-program operation is executed to restore a threshold voltage of the memory cells to a higher value than a depletion verify voltage value. The method may include identifying a first value of the depletion verify voltage, executing the re-program operation using the value of the depletion verify voltage, and verifying the array of re-programmed cells for reliability in a read mode. If the outcome of the verifying step is favorable, the re-program operation is terminated as successful. Otherwise, the value of the depletion verify voltage is modified, and the re-program operation is again executed using the modified value of the depletion verify voltage as adjusted for the actual operating conditions of the memory array.

Abstract: A method corrects the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the present correction method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical base other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary base, to a base n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a base n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical base used for the conversion.

Abstract: A method of modifying the threshold voltages of a plurality of non-volatile memory cells, for example, flash EEPROM memory cells, after an erasure operation, is described. In order to perform the equalization quickly and to optimize the use of the voltage supplies for biasing the columns, the method provides for the following steps: connecting all of the column lines to a voltage supply, monitoring the supply voltage, and applying, to all of the row lines, a voltage variable from a predetermined minimum value to a predetermined maximum value, the rate of change being regulated to maintain the supply voltage of the column lines at a substantially constant, predetermined value. The same method can be used for reliable and quick programming of a memory of the flash EEPROM type, or of another type.

Abstract: A method of re-programming an array of non-volatile memory cells after an erase operation is provided where a re-program operation is executed to restore a threshold voltage of the memory cells to a higher value than a depletion verify voltage value. The method may include identifying a first value of the depletion verify voltage, executing the re-program operation using the value of the depletion verify voltage, and verifying the array of re-programmed cells for reliability in a read mode. If the outcome of the verifying step is favorable, the re-program operation is terminated as successful. Otherwise, the value of the depletion verify voltage is modified, and the re-program operation is again executed using the modified value of the depletion verify voltage as adjusted for the actual operating conditions of the memory array.

Abstract: A method of modifying the threshold voltages of a plurality of non-volatile memory cells, for example, flash EEPROM memory cells, after an erasure operation, is described. In order to perform the equalization quickly and to optimize the use of the voltage supplies for biasing the columns, the method provides for the following steps: connecting all of the column lines to a voltage supply, monitoring the supply voltage, and applying, to all of the row lines, a voltage variable from a predetermined minimum value to a predetermined maximum value, the rate of change being regulated to maintain the supply voltage of the column lines at a substantially constant, predetermined value. The same method can be used for reliable and quick programming of a memory of the flash EEPROM type, or of another type.