Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.

Abstract: In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells to store one of N different values, where Nis a number of different levels that can be stored in any of the analog neural non-volatile memory cells; measuring a current drawn by the plurality of analog neural non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.

Abstract: Examples of programming circuits and methods are provided. In one example, an adjustable programming circuit comprises a first adjustable voltage divider; a second adjustable voltage divider; a first operational amplifier, wherein an output terminal of the first operational amplifier provides a first programming voltage; and a second operational amplifier, wherein the first input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier and the first input terminal of the second operational amplifier is coupled to the second output terminal of the first adjustable voltage divider.

Abstract: A diode comprises a semiconductor substrate, an n-well formed in the semiconductor substrate, a p-well formed in the semiconductor substrate that is spaced apart from the n-well, a first isolation region formed in the n-well, a first electrode formed in direct contact with the n-well and formed of a metal material, a first heavily doped region formed in the n-well and having a dopant concentration greater than a dopant concentration of the n-well, a second electrode formed in direct contact with the first heavily doped region, a second isolation region formed in the semiconductor substrate and between the n-well and the p-well, a second heavily doped region formed in the p-well and having a dopant concentration greater than a dopant concentration of the p-well, and a third electrode formed in direct contact with the second heavily doped region.

Abstract: Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a system comprises an array of resistive random access memory (RRAM) units arranged in rows and columns; and a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array, wherein the first RRAM unit comprises a first select transistor coupled to a first set of one or more RRAM cells and the second RRAM unit comprises a second select transistor coupled to a second set of one or more RRAM cells.

Abstract: Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a read bias generator comprises a bias transistor, a feedback loop, a replica resistor, and a reference unit. Optionally, the read bias generator is coupled to an array of RRAM units.

Abstract: Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In one example, an artificial neural network system comprises an analog array of non-volatile memory cells arranged into rows and columns; a digital array of non-volatile memory cells arranged into rows and columns, the analog array and the digital array fabricated on a same semiconductor die; a first plurality of bit lines, wherein each bit line in the first plurality of bit lines is coupled to a column of non-volatile memory cells in the analog array; and a second plurality of bit lines, wherein each bit line in the second plurality of bit lines is coupled to a column of non-volatile memory cells in the digital array and the second plurality of bit lines are disconnected from the first plurality of bit lines.

Abstract: In one example, a method for erasing a non-volatile memory cell comprises performing a pre-erase sequence comprising applying voltages in a step pattern to a terminal of the non-volatile memory cell; and performing an erase sequence comprising applying a plurality of pulses of increasing voltages to the terminal of the non-volatile memory cell.

Abstract: Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

Abstract: In one example, a high voltage generation block comprises a temperature sensor to sense an operating temperature and output a temperature output, a trim circuit to receive a trim enable circuit and the temperature output and to generate oscillator trim bits, a charge pump oscillator to generate an oscillating signal in response to the oscillator trim bits and a feedback signal, a charge pump to receive the oscillating signal and to generate a pumped voltage, and a charge pump regulator to receive the pumped voltage and to generate the feedback signal and a high voltage output.

Abstract: In one example, a system comprises an array of resistive random access memory (RRAM) units arranged in rows and columns; and a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array.

Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m?2u, n?2v, and p?2t.

Abstract: Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.

Abstract: In one example, an analog neural memory system comprises a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a bit line terminal, a control gate terminal, and a word line terminal; a plurality of bit lines, wherein each of the plurality of bit lines is coupled to the bit line terminals of a column of memory cells; a plurality of control gate lines, wherein each of the plurality of control gate lines is coupled to the control gate terminals of a row of memory cells; and a plurality of word lines, wherein each of the plurality of word lines is coupled to the word line terminals of a row of memory cells; wherein the plurality of control gate lines are parallel to the plurality of bit lines and perpendicular to the plurality of word lines.

Abstract: In one example, a method comprises determining a logarithmic slope factor for a selected analog non-volatile memory cell in an array of analog non-volatile memory cells while the selected analog non-volatile memory cell is operating in a sub-threshold region; storing the logarithmic slope factor; determining a linear slope factor for the selected analog non-volatile memory cell while the selected analog non-volatile memory cell is operating in a linear region; storing the linear slope factor; and utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected analog non-volatile memory cell to a target current.

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.