Patents by Inventor Anh Ly

Anh Ly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20210020255
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20210019608
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Analog neural memory system for deep learning neural network comprising multiple vector-by-matrix multiplication arrays and shared components
    Patent number: 10896368
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. In one embodiment, the analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication systems, each vector-by-matrix multiplication system comprising an array of memory cells, a low voltage row decoder, a high voltage row decoder, and a low voltage column decoder; a plurality of output blocks, each output block providing an output in response to at least one of the plurality of vector-by-matrix multiplication systems; and a shared verify block configured to concurrently perform a verify operation after a program operation on two or more of the plurality of vector-by-matrix systems.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: January 19, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Analog neural memory system for deep learning neural network comprising multiple vector-by-matrix multiplication arrays and shared components
    Patent number: 10860918
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. The analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication arrays and various components shared by those arrays. The shared components include high voltage generation blocks, verify blocks, and testing blocks. The analog neuromorphic memory system optionally is used within a long short term memory system or a gated recurrent unit system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 8, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Charge pump for use in non-volatile flash memory devices
    Patent number: 10847227
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 24, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Dynamic modification of programming duration based on number of cells to be programmed in analog neural memory array in deep learning artificial neural network
    Patent number: 10839907
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, the duration of a programming voltage can change as the number of cells to be programmed changes.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200342938
    Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 29, 2020
    Inventors: HIEU VAN TRAN, THUAN VU, STANLEY HONG, STEPHEN TRINH, ANH LY, HAN TRAN, KHA NGUYEN, HIEN PHAM
  • Adaptive high voltage circuitry and methods for programming operations in an analog neural memory array in a deep learning artificial neural network
    Patent number: 10790022
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. The system can modify a high voltage signal applied to an array of cells during a programming operation as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: September 29, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • FLASH MEMORY CELL AND ASSOCIATED HIGH VOLTAGE ROW DECODER
    Publication number: 20200286569
    Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • ANALOG NEURAL MEMORY SYSTEM FOR DEEP LEARNING NEURAL NETWORK COMPRISING MULTIPLE VECTOR-BY-MATRIX MULTIPLICATION ARRAYS AND SHARED COMPONENTS
    Publication number: 20200272886
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. In one embodiment, the analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication systems, each vector-by-matrix multiplication system comprising an array of memory cells, a low voltage row decoder, a high voltage row decoder, and a low voltage column decoder; a plurality of output blocks, each output block providing an output in response to at least one of the plurality of vector-by-matrix multiplication systems; and a shared verify block configured to concurrently perform a verify operation after a program operation on two or more of the plurality of vector-by-matrix systems.
    Type: Application
    Filed: January 18, 2020
    Publication date: August 27, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof
    Patent number: 10755779
    Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 25, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Flash memory cell and associated decoders
    Patent number: 10741265
    Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 11, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • ALGORITHMS AND CIRCUITRY FOR VERIFYING A VALUE STORED DURING A PROGRAMMING OPERATION OF A NON-VOLATILE MEMORY CELL IN AN ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200242461
    Abstract: Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits. Circuity, such as an adjustable reference current source, for implementing the algorithms are disclosed.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 30, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
  • Precision Programming Circuit For Analog Neural Memory In Deep Learning Artificial Neural Network
    Publication number: 20200242460
    Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 30, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
  • Adjustable current sink to draw compensation current from high voltage generation circuitry during programming operation of analog neural memory in deep learning artificial neural network
    Patent number: 10650893
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: May 12, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Charge Pump For Use In Non-volatile Flash Memory Devices
    Publication number: 20200118632
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 16, 2020
    Inventors: HIEU VAN TRAN, ANH LY, THUAN VU, KHA NGUYEN, HIEN PHAM, STANLEY HONG, STEPHEN T. TRINH
  • ANALOG NEURAL MEMORY SYSTEM FOR DEEP LEARNING NEURAL NETWORK COMPRISING MULTIPLE VECTOR-BY-MATRIX MULTIPLICATION ARRAYS AND SHARED COMPONENTS
    Publication number: 20200065650
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. The analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication arrays and various components shared by those arrays. The shared components include high voltage generation blocks, verify blocks, and testing blocks. The analog neuromorphic memory system optionally is used within a long short term memory system or a gated recurrent unit system.
    Type: Application
    Filed: November 6, 2018
    Publication date: February 27, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • ADAPTIVE HIGH VOLTAGE CIRCUITRY AND METHODS FOR PROGRAMMING OPERATIONS IN AN ANALOG NEURAL MEMORY ARRAY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200058357
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. The system can modify a high voltage signal applied to an array of cells during a programming operation as the number of cells being programmed changes.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 20, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Dynamic Modification Of Programming Duration Based On Number Of Cells To Be Programmed In Analog Neural Memory Array In Deep Learning Artificial Neural Network
    Publication number: 20200058356
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, the duration of a programming voltage can change as the number of cells to be programmed changes.
    Type: Application
    Filed: August 24, 2019
    Publication date: February 20, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • ADJUSTABLE CURRENT SINK TO DRAW COMPENSATION CURRENT FROM HIGH VOLTAGE GENERATION CIRCUITRY DURING PROGRAMMING OPERATION OF ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200051635
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 13, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do