Patents by Inventor Anilkumar Chandolu

Anilkumar Chandolu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190326260
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Applicant: Micron Technology, Inc.
    Inventors: SAMEER S. VADHAVKAR, XIAO LI, ANILKUMAR CHANDOLU
  • Patent number: 10438928
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Anilkumar Chandolu
  • Publication number: 20190252338
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Publication number: 20190206766
    Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Anilkumar Chandolu, Wayne H. Huang, Sameer S. Vadhavkar
  • Publication number: 20190172817
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: SAMEER S. VADHAVKAR, XIAO LI, ANILKUMAR CHANDOLU
  • Publication number: 20190157246
    Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Inventor: Anilkumar Chandolu
  • Patent number: 10276529
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Patent number: 10192852
    Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Anilkumar Chandolu
  • Publication number: 20180026015
    Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.
    Type: Application
    Filed: October 3, 2017
    Publication date: January 25, 2018
    Inventor: Anilkumar Chandolu
  • Publication number: 20170358547
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 14, 2017
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Publication number: 20170352633
    Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Inventors: Giorgio Mariottini, Sameer Vadhavkar, Wayne Huang, Anilkumar Chandolu, Mark Bossler
  • Patent number: 9818728
    Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 14, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Anilkumar Chandolu
  • Patent number: 9780052
    Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Giorgio Mariottini, Sameer Vadhavkar, Wayne Huang, Anilkumar Chandolu, Mark Bossler
  • Patent number: 9768134
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Publication number: 20170077052
    Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 16, 2017
    Inventors: Giorgio Mariottini, Sameer Vadhavkar, Wayne Huang, Anilkumar Chandolu, Mark Bossler
  • Publication number: 20160268235
    Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventor: Anilkumar Chandolu
  • Publication number: 20160247742
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Application
    Filed: February 19, 2015
    Publication date: August 25, 2016
    Inventors: SAMEER S. VADHAVKAR, XIAO LI, ANILKUMAR CHANDOLU
  • Publication number: 20160225731
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Patent number: 9397078
    Abstract: Semiconductor device assemblies with underfill containment cavities are disclosed herein. In one embodiment, a semiconductor device assembly can include a first semiconductor die having a base region formed from a substrate material, a recessed surface along the base region, a peripheral region formed from the substrate material and projecting from the base region, and a sidewall surface along the peripheral region and defining a cavity with the sidewall surface in the peripheral region. The semiconductor device assembly further includes a thermal transfer structure attached to the peripheral region of the first die adjacent the cavity, and an underfill material at least partially filling the cavity and including a fillet between the peripheral region and the stack of second semiconductor dies.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 19, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Wayne H. Huang, Sameer S. Vadhavkar
  • Patent number: 9356009
    Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 31, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Anilkumar Chandolu