Abstract: A structure includes a semiconductor substrate, a buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer.

Abstract: Keyword bids determined from sparse data are described. Initially, a portfolio optimization platform identifies which keywords included in a portfolio of keywords are low-impression keywords. This platform trains a machine learning model to generate bids for the low-impression keywords with historical data from a search engine. In particular, the platform trains this machine learning model according to an algorithm suited for training with sparse amounts of data, e.g., a temporal difference learning algorithm. In contrast, the platform uses different models, trained according to different algorithms than the low-impression keyword model, to generate bids for keywords determined not to be low-impression keywords. Once the low-impression keyword model is trained offline, the platform deploys the model for use online to generate actual bids for the low-impression keywords and submits them to the search engine.

Abstract: A structure includes a semiconductor substrate, a buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer.

Abstract: A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

Abstract: A dynamically correcting cache memory is capable of correcting itself by dynamically reflecting any modifications inflicted upon the data/information to be stored therein. Further, the cache memory is refreshed at predetermined time intervals and also based on predetermined criteria, thereby ensuring a high cache hit rate. The dynamically correcting cache memory is bypassed for certain user queries prioritized based on a predetermined criteria. The dynamically correcting cache manages an inventory shared between multiple non-cooperative web-based, computer-implemented platforms. The dynamically correcting cache is directed to reducing caching errors in web based computer implemented platforms. The dynamically correcting cache responds to rapid changes associated with (online) behavior of users accessing web based computer implemented platforms by dynamically configuring TTL (Time-To-Live) values, in order to ensure that the data/information stored in the cache memory remains accurate.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure has a semiconductor channel region composed of a first semiconductor material that (i) is epitaxial with and (ii) is lattice-matched with a second semiconductor material. The semiconductor structure has, at a first end of the semiconductor channel region, a first source/drain region composed of a third semiconductor material that is lattice-mismatched to both the first semiconductor material and the second semiconductor material.

Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Abstract: A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

Abstract: A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed on the semiconductor substrate, an oxide layer disposed on the buffer layer, and a fin including a semiconductor material disposed on the oxide layer. The fin and the buffer layer are epitaxially aligned to the semiconductor substrate.

Abstract: A photosensitive laminate (121) includes an optically clear polymer film (123) comprising a thermoplastic polymer, and further having a first surface (124) and a second surface (125) opposite the first surface. An organic image sensor layer (126) disposed on at least a portion of the first surface (124) of the optically clear polymer film. A glass layer (122) is laminated directly onto the organic image sensor layer (126) and the first surface (124) of the optically clear polymer film, wherein no adhesive is disposed between the first surface of the optically clear polymer film (124) and the glass layer (122). A method of manufacturing the photosensitive laminate and image sensor devices are also described.

Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.