Patents by Inventor Anirban Basu

Anirban Basu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9227855
    Abstract: A system for disinfecting a water sample includes a pipe having an inlet for engaging a source of the water sample, a storage reservoir connected to an outlet of the pipe for holding the water sample, an array of photovoltaic cells coupled to the pipe for converting solar radiation into a current, and an array of light emitting diodes coupled to the pipe and powered by the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation. A method for disinfecting a fluent water sample includes generating a current using an array of photovoltaic cells, using the current to power an array of light emitting diodes, wherein the array of light emitting diodes emits a germicidal wavelength of radiation, and exposing the fluent water sample to the radiation while transporting the fluent water sample from a source to a storage reservoir.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Stephen W. Bedell, Wilfried E. Haensch, Davood Shahrjerdi
  • Patent number: 9224866
    Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anirban Basu, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
  • Publication number: 20150372141
    Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 24, 2015
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Publication number: 20150357417
    Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Anirban Basu, Guy M. Cohen
  • Publication number: 20150340495
    Abstract: Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 26, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 9196711
    Abstract: Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Guy M. Cohen, Amlan Majumdar
  • Publication number: 20150325650
    Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
    Type: Application
    Filed: July 8, 2015
    Publication date: November 12, 2015
    Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20150318303
    Abstract: Disposable gate structures and a planarization dielectric layer are formed over doped semiconductor material portions on a crystalline insulator layer. Gate cavities are formed by removing the disposable gate structures selective to the planarization dielectric layer. Doped semiconductor material portions are removed from underneath the gate cavities to provide pairs of source and drain regions separated by a gate cavity. Within a first gate cavity, a faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer, while a second gate is temporarily coated with an amorphous material layer. A contoured semiconductor region is epitaxially grown on the faceted crystalline dielectric material portion in the first gate cavity, while a planar semiconductor region is epitaxially grown in the second gate cavity. The semiconductor regions can provide at least one contoured channel region and at least one planar channel region.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 5, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Pouya Hashemi
  • Publication number: 20150311302
    Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.
    Type: Application
    Filed: June 15, 2015
    Publication date: October 29, 2015
    Inventors: Anirban Basu, Guy Cohen, Amlan Majumdar
  • Patent number: 9159822
    Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9150434
    Abstract: Disinfecting a sample of water includes generating a current using an array of photovoltaic cells, using the current to power an array of light emitting diodes, wherein the array of light emitting diodes emits a germicidal wavelength of radiation, and exposing the sample of water to the radiation. Another method for disinfecting a sample of water includes placing the sample of water within a container, wherein the container includes an array of photovoltaic cells encircling an exterior wall of the container and an array of light emitting diodes encircling an interior wall of the container, placing the container in a location exposed to solar radiation, converting the solar radiation to a current using the array of photovoltaic cells, and powering the array of light emitting diodes using the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation sufficient to disinfect the sample of water.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Stephen W. Bedell, Devendra K. Sadana
  • Publication number: 20150263102
    Abstract: A structure and method for forming a substrate, a buffer layer disposed on the substrate, an oxide layer disposed on the buffer layer, and a fin comprising a semiconductor material disposed on the oxide layer.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Guy M. Cohen, Amlan Majumdar, Yu Zhu
  • Patent number: 9136357
    Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: September 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Guy Cohen, Amlan Majumdar
  • Publication number: 20150255568
    Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Applicant: International Business Machines Corporation
    Inventors: ANIRBAN BASU, Guy Cohen, Amlan Majumdar
  • Publication number: 20150255567
    Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Guy Cohen, Amlan Majumdar
  • Publication number: 20150255570
    Abstract: Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Guy M. Cohen, Amlan Majumdar
  • Patent number: 9129825
    Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer. A contoured channel region is epitaxially grown on the faceted crystalline dielectric material portion. The contoured channel region increases the distance that charge carriers travel relative to a separation distance between the source region and the drain region.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: September 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Pouya Hashemi, Ali Khakifirooz
  • Publication number: 20150248835
    Abstract: Systems and methods for providing a user with information on spaces in which to park a vehicle are provided. A method for providing a user with information on spaces in which to park a vehicle, comprises identifying one or more spaces in which to park the vehicle, selecting valid spaces from the identified one or more spaces based on a validation criteria, and ranking the valid spaces and providing a ranked list of the valid spaces to the user, wherein the identifying, selecting, ranking and providing steps are performed by a computer system comprising a memory and at least one processor coupled to the memory.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 3, 2015
    Applicant: International Business Machines Corporation
    Inventors: Aleksandr Y. Aravkin, Anirban Basu, Dimitri Kanevsky, Tara N. Sainath, Premal Y. Shah
  • Publication number: 20150243773
    Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9070770
    Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Guy Cohen, Amlan Majumdar