Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. The selective low temperature epitaxy process can be performed at a temperature lower than 600° C., thereby limiting diffusion of materials within the multi-quantum well and avoiding segregation of indium within the multi-quantum well. The light-emitting diode can generate a radiation of a wide range including blue and green lights in the visible wavelength range.

Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer.

Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer. A contoured channel region is epitaxially grown on the faceted crystalline dielectric material portion. The contoured channel region increases the distance that charge carriers travel relative to a separation distance between the source region and the drain region.

Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer.

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.

Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.

Abstract: A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor.

Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.

Abstract: A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.

Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well, and an n-doped GaN portion is formed on an insulator substrate. The p-doped GaN portion may be formed above, or below, the multi-quantum-well. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a top surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. Metallization is performed on a portion of the elemental semiconductor material portions to form an electrical contact structure that provides effective electrical contact to the p-doped GaN portion through the elemental semiconductor material portion.

Abstract: A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor.

Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.

Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.

Abstract: A metallization scheme employing a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and second refractory metal barrier layer are free of nitrogen, and thus, do not introduce additional nitrogen into the compound semiconductor layer, while allowing diffusion of the Group IIIA element to form locally doped regions underneath the source region and the drain region. Ohmic contacts may be formed at a temperature as low as about 500° C. This enables fabrication of FET whose source and drain are self-aligned to the gate.

Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.

Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well, and an n-doped GaN portion is formed on an insulator substrate. The p-doped GaN portion may be formed above, or below, the multi-quantum-well. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a top surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. Metallization is performed on a portion of the elemental semiconductor material portions to form an electrical contact structure that provides effective electrical contact to the p-doped GaN portion through the elemental semiconductor material portion.

Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well, and an n-doped GaN portion is formed on an insulator substrate. The p-doped GaN portion may be formed above, or below, the multi-quantum-well. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a top surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. Metallization is performed on a portion of the elemental semiconductor material portions to form an electrical contact structure that provides effective electrical contact to the p-doped GaN portion through the elemental semiconductor material portion.

Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. The selective low temperature epitaxy process can be performed at a temperature lower than 600° C., thereby limiting diffusion of materials within the multi-quantum well and avoiding segregation of indium within the multi-quantum well. The light-emitting diode can generate a radiation of a wide range including blue and green lights in the visible wavelength range.