Patents by Inventor Ankur Shah

Ankur Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11403805
    Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Travis Schluessler, Zack Waters, Michael Apodaca, Daniel Johnston, Jason Surprise, Prasoonkumar Surti, Subramaniam Maiyuran, Peter Doyle, Saurabh Sharma, Ankur Shah, Murali Ramadoss
  • Publication number: 20220222185
    Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.
    Type: Application
    Filed: April 2, 2022
    Publication date: July 14, 2022
    Applicant: Intel Corporation
    Inventors: Vidhya Krishnan, Siddhartha Chhabra, David Puffer, Ankur Shah, Daniel Nemiroff, Utkarsh Y. Kakaiya
  • Publication number: 20220222340
    Abstract: Security and support for trust domain operation is described. An example of a method includes processing, at an accelerator, one or more compute workloads received from a host system; upon receiving a notification that a trust domain has transitioned to a secure state, transition an original set of privileges for the accelerator to a downgraded set of privileges; upon receiving a command from the host system for the trust domain, processing the command in accordance with the trust domain; and upon receiving a request from the host system to access a register, for a register included in an allowed list of registers for access, allow access to the register, and, for a register that is not within the allowed list of registers for access, disallowing access to the register.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Applicant: Intel Corporation
    Inventors: Vidhya Krishnan, Ankur Shah, Bryan White, Daniel Nemiroff, David Puffer, Julien Carreno, Scott Janus, Ravi Sahita, Hema Nalluri, Utkarsh Y. Kakaiya
  • Patent number: 11385952
    Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 12, 2022
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Bryan White, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Mahesh Natu
  • Patent number: 11384387
    Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 12, 2022
    Assignee: GEN-PROBE INCORPORATED
    Inventors: Mehrdad R. Majlessi, Ankur Shah, Amber Hillius, Pamela Douglass, Daniel Kolk
  • Publication number: 20220138286
    Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.
    Type: Application
    Filed: December 23, 2020
    Publication date: May 5, 2022
    Applicant: Intel Corporation
    Inventors: David Zage, Scott Janus, Ned M. Smith, Vidhya Krishnan, Siddhartha Chhabra, Rajesh Poornachandran, Tomer Levy, Julien Carreno, Ankur Shah, Ronald Silvas, Aravindh Anantaraman, David Puffer, Vedvyas Shanbhogue, David Cowperthwaite, Aditya Navale, Omer Ben-Shalom, Alex Nayshtut, Xiaoyu Ruan
  • Patent number: 11321262
    Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Hema Chand Nalluri, Ankur Shah, Joydeep Ray, Aditya Navale, Altug Koker, Murali Ramadoss, Niranjan L. Cooray, Jeffery S. Boles, Aravindh Anantaraman, David Puffer, James Valerio, Vasanth Ranganathan
  • Patent number: 11308680
    Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Ankur Shah, Matthew Callaway, Vivek Garg, Rajeev K Nalawadi, James Varga
  • Publication number: 20220114096
    Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.
    Type: Application
    Filed: March 14, 2020
    Publication date: April 14, 2022
    Applicant: Intel Corporation
    Inventors: Lakshminarayanan Striramassarma, Prasoonkumar Surti, Varghese George, Ben Ashbaugh, Aravindh Anantaraman, Valentin Andrei, Abhishek Appu, Nicolas Galoppo Von Borries, Altug Koker, Mike Macpherson, Subramaniam Maiyuran, Nilay Mistry, Elmoustapha Ould-Ahmed-Vall, Selvakumar Panneer, Vasanth Ranganathan, Joydeep Ray, Ankur Shah, Saurabh Tangri
  • Publication number: 20220098647
    Abstract: Compositions, methods, kits, and uses are provided for detecting or quantifying a Group A Streptococcus (GAS) nucleic acid, e.g., using nucleic acid amplification and hybridization assays.
    Type: Application
    Filed: March 20, 2020
    Publication date: March 31, 2022
    Applicant: Gen-Probe Incorporated
    Inventors: Sree Divya Panuganti, Ankur Shah
  • Publication number: 20220075746
    Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 10, 2022
    Applicant: Intel Corporation
    Inventors: Hema Chand Nalluri, Ankur Shah, Joydeep Ray, Aditya Navale, Altug Koker, Murali Ramadoss, Niranjan L. Cooray, Jeffery S. Boles, Aravindh Anantaraman, David Puffer, James Valerio, Vasanth Ranganathan
  • Publication number: 20220074002
    Abstract: Oligomer nucleotides, compositions, methods, kits, and uses are provided for detecting or quantifying a Human Cytomegalovirus virus 1 (CMV (human herpesvirus 5, HHV5) nucleic acid, e.g., using nucleic acid amplification and hybridization assays. Multiphase amplification of a CMV target sequence is also described. The oligomer nucleotides, compositions, methods, kits, and uses can be used to amplify and/or detect the UL56 gene of CMV.
    Type: Application
    Filed: August 21, 2019
    Publication date: March 10, 2022
    Inventors: Paul Darby, Siobhan Miick, Jo Ann Jackson, Hee Cheol Kim, Amber Hillius, Ankur Shah
  • Publication number: 20220017980
    Abstract: Disclosed are oligonucleotides, oligonucleotide compositions, kits, methods, formulations, and reaction mixtures that provide for sensitive and specific detection of a target nucleic acid sequence, or amplicon generated from a target nucleic acid sequence, of Varicella-Zoster Virus (VZV1 (if present) in a sample. The oligonucleotides, compositions, kits, methods, formulations, and reaction mixtures can be used to detect the presence of VZV in a sample. The oligonucleotides, compositions, kits, methods, formulations, and reaction mixtures can also be used to amplify specific target nucleic acid regions of VZV.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 20, 2022
    Applicant: GEN-PROBE INCORPORATED
    Inventors: Marcela Alejandra CARVALLO PINTO, Amber Jean HILLIUS, Ankur SHAH
  • Publication number: 20220010388
    Abstract: Oligomer nucleotides, compositions, methods, kits, and uses are provided for detecting or quantifying a human polyomavirus BK virus (BKV) nucleic acid, e.g., using nucleic acid amplification and hybridization assays.
    Type: Application
    Filed: October 22, 2019
    Publication date: January 13, 2022
    Inventors: Ankur Shah, Meghna Yadav
  • Publication number: 20210349831
    Abstract: Described herein is an accelerator device having a cache memory for which limits may be specified for a memory allocation according to a class of service associated with a thread, application, or virtual machine that created the memory allocation. The limits can include a specific set of enumerated cache ways that are designated as eligible to cache data for memory allocations associated with a class of service.
    Type: Application
    Filed: June 25, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: NIRANJAN L. COORAY, ARAVINDH ANANTARAMAN, K. PATTABHIRAMAN, ANKUR SHAH
  • Publication number: 20210332449
    Abstract: Disclosed are compositions, methods, and kits that can be used to Epstein-Ban virus (EBV) in a sample undergoing testing. Nucleic acids of EBV can be isolated, amplified and detected with specificity by real-time PCR, and without interference from non-EBV organisms. In some embodiments, nucleic acids used for amplification are isolated from human blood, or blood products. Nucleic acid isolation, amplification and detection steps can all be carried out using an automated instrument.
    Type: Application
    Filed: August 1, 2019
    Publication date: October 28, 2021
    Inventors: Ankur SHAH, Jian Yu FUNG
  • Patent number: 11157431
    Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Bryan R. White, Aravindh Anantaraman, Ankur Shah, Altug Koker, David Puffer, Aditya Navale
  • Patent number: 11127106
    Abstract: Methods and apparatus relating to techniques for runtime flip stability characterization are described. In an embodiment, logic circuitry determines the amount of work to be performed by a processor to render a pattern during each of a plurality of Vertical blank (Vblank) intervals. Memory stores information corresponding to a workload to be executed by the processor during each of the plurality of Vblank intervals. An operating frequency of the processor may then be modified based at least in part on analysis of the stored information to indicate which of the plurality of Vblank intervals would provide an improved stability for rendering the pattern. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 21, 2021
    Assignee: INTEL CORPORATION
    Inventors: Murali Ramadoss, Ankur Shah, Marc Beuchat
  • Publication number: 20210279181
    Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 9, 2021
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Aditya Navale, Ankur Shah, Murali Ramadoss, Ben Ashbaugh, Ronald Silvas
  • Publication number: 20210272349
    Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 2, 2021
    Applicant: Intel Corporation
    Inventors: TRAVIS SCHLUESSLER, ZACK WATERS, MICHAEL APODACA, DANIEL JOHNSTON, JASON SURPRISE, PRASOONKUMAR SURTI, SUBRAMANIAM MAIYURAN, PETER DOYLE, SAURABH SHARMA, ANKUR SHAH, MURALI RAMADOSS