Patents by Inventor Ankur Shah
Ankur Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11816040Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.Type: GrantFiled: April 2, 2022Date of Patent: November 14, 2023Assignee: INTEL CORPORATIONInventors: Vidhya Krishnan, Siddhartha Chhabra, David Puffer, Ankur Shah, Daniel Nemiroff, Utkarsh Y. Kakaiya
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Publication number: 20230306552Abstract: Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.Type: ApplicationFiled: May 27, 2022Publication date: September 28, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, David Puffer, Ankur Shah, Alan Previn Teres Alexis, Satyeshwar Singh
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Publication number: 20230298128Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table.Type: ApplicationFiled: June 24, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Puffer, Ankur Shah, Niranjan Cooray, Aditya Navale, David Cowperthwaite
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Publication number: 20230297421Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, Kenneth Daxer, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Hema Chand Nalluri, Jeffery S. Boles, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala, Michael Apodaca
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Publication number: 20230297440Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, Kenneth Daxer, Jeffery S. Boles, Hema Chand Nalluri, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala
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Publication number: 20230298129Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.Type: ApplicationFiled: June 24, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Puffer, Ankur Shah, Niranjan Cooray, David Cowperthwaite, Aditya Navale
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Publication number: 20230298125Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Hema Chand Nalluri, Jeffery S. Boles, David Cowperthwaite, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Ankur Shah, Vidhya Krishnan, Kritika Bala, Aravindh Anantaraman, Michael Apodaca, Kenneth Daxer
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Publication number: 20230297526Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.Type: ApplicationFiled: June 3, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Puffer, Ankur Shah, Niranjan Cooray, Bryan White, Balaji Vembu, Hema Chand Nalluri, Kritika Bala
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Patent number: 11748283Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.Type: GrantFiled: June 3, 2022Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: David Puffer, Ankur Shah, Niranjan Cooray, Bryan White, Balaji Vembu, Hema Chand Nalluri, Kritika Bala
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Publication number: 20230244609Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: ApplicationFiled: December 30, 2022Publication date: August 3, 2023Applicant: Intel CorporationInventors: ZACK S. WATERS, TRAVIS SCHLUESSLER, MICHAEL APODACA, ANKUR SHAH
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Patent number: 11710269Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: GrantFiled: July 28, 2022Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Travis Schluessler, Zack Waters, Michael Apodaca, Daniel Johnston, Jason Surprise, Prasoonkumar Surti, Subramaniam Maiyuran, Peter Doyle, Saurabh Sharma, Ankur Shah, Murali Ramadoss
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Patent number: 11704181Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.Type: GrantFiled: June 24, 2022Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Balaji Vembu, Bryan White, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Mahesh Natu
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Publication number: 20230203572Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, Metapneumovirus, and/or Rhinovirus nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.Type: ApplicationFiled: December 27, 2022Publication date: June 29, 2023Inventors: Mehrdad R. MAJLESSI, Ankur SHAH, Amber HILLIUS, Pamela DOUGLASS, Daniel KOLK
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Publication number: 20230203571Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, Metapneumovirus, and/or Rhinovirus nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.Type: ApplicationFiled: December 27, 2022Publication date: June 29, 2023Inventors: Mehrdad R. MAJLESSI, Ankur SHAH, Amber HILLIUS, Pamela DOUGLASS, Daniel KOLK
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Patent number: 11657561Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.Type: GrantFiled: April 12, 2022Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Ankur Shah, Matthew Callaway, Vivek Garg, Rajeev K. Nalawadi, James Varga
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Publication number: 20230109990Abstract: One embodiment provides a graphics processor including an active base die including a fabric interconnect and a chiplet including a switched fabric, wherein the chiplet couples with the active base die via an array of interconnect structures, the array of interconnect structures couple the fabric interconnect with the switched fabric, and the chiplet includes a first modular interconnect configured to couple a block of graphics processing resources to the switched fabric and a second modular interconnect configured to couple a memory subsystem with the switched fabric and the block of graphics processing resources, the memory interconnect including a set of memory controllers and a set of physical interfaces.Type: ApplicationFiled: October 7, 2021Publication date: April 13, 2023Applicant: Intel CorporationInventors: Lakshminarayana Pappu, Altug Koker, Aditya Navale, Prasoonkumar Surti, Ankur Shah, Joydeep Ray, Naveen Matam
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Publication number: 20230113953Abstract: In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.Type: ApplicationFiled: October 6, 2022Publication date: April 13, 2023Applicant: Intel CorporationInventors: Lakshminarayana Pappu, Phani Kumar Kandula, Ali Ibrahim, Murali Ramadoss, Ankur Shah
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Publication number: 20230087588Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, Metapneumovirus, and/or Rhinovirus nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.Type: ApplicationFiled: August 17, 2022Publication date: March 23, 2023Inventors: Mehrdad R. MAJLESSI, Ankur Shah, Amber Hillius, Pamela Douglass, Daniel Kolk
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Patent number: 11580027Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: GrantFiled: February 26, 2020Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Zack S. Waters, Travis Schluessler, Michael Apodaca, Ankur Shah
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Publication number: 20230039853Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Intel CorporationInventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler