Abstract: Disclosed are compositions, methods, and kits that can be used to Epstein-Barr virus (EBV) in a sample undergoing testing. Nucleic acids of EBV can be isolated, amplified and detected with specificity, and without interference from non-EBV organisms. In some embodiments, nucleic acids used for amplification are isolated from human blood, or blood products. Nucleic acid isolation, amplification and detection steps can all be carried out using an automated instrument.

Abstract: Method of preparing a biological sample appropriate for use in a subsequent in vitro nucleic acid amplification reaction. A biological sample is combined with an alkaline composition that lyses cells and denatures DNA to create a first liquid composition. The first liquid composition is then mixed with a buffer, a detergent, and a solid support that captures DNA to create a second liquid composition. The buffer, detergent, and solid support can be delivered as components of a single reagent. Captured DNA strands can be used as templates in subsequently performed nucleic acid amplification and detection reactions with improved sensitivity.

Abstract: Disclosed are compositions, methods, and kits that can be used to Epstein-Ban virus (EBV) in a sample undergoing testing. Nucleic acids of EBV can be isolated, amplified and detected with specificity by real-time PCR, and without interference from non-EBV organisms. In some embodiments, nucleic acids used for amplification are isolated from human blood, or blood products. Nucleic acid isolation, amplification and detection steps can all be carried out using an automated instrument.

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die on a carrier substrate and affixing a rigid-flex sub-assembly on the semiconductor die. The rigid-flex sub-assembly includes a rigid portion and a flex portion having a conductive trace. A distal region of the flex portion is bent such that the bent distal region is not coplanar with the rigid portion. An encapsulant encapsulates at least a portion of the semiconductor die and the rigid-flex sub-assembly.

Abstract: Oligomer nucleotides, compositions, methods, kits, and uses are provided for detecting or quantifying a human polyomavirus BK virus (BKV) nucleic acid, e.g., using nucleic acid amplification and hybridization assays.

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Abstract: Oligomer nucleotides, compositions, methods, kits, and uses are provided for detecting or quantifying a human polyomavirus BK virus (BKV) nucleic acid, e.g., using nucleic acid amplification and hybridization assays.

Abstract: Oligomer nucleotides, compositions, methods, kits, and uses are provided for detecting or quantifying a human polyomavirus BK virus (BKV) nucleic acid, e.g., using nucleic acid amplification and hybridization assays.

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Abstract: A device package is formed form a volume of molding material that encapsulates a component. Edges of the component are protected by encapsulated areas formed above the edges by a filler material prior to molding the component. The molding material also encapsulates the filler material and positioning of the filler material defines a location and dimensions of an aperture in the molding material that exposes a portion of a top surface of the component.

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: Embodiments described herein provide a system of concurrent compute queues that enable the scheduling of a large number of compute contexts simultaneously on graphics processor hardware. One embodiment provides an apparatus comprising a system interface and a general-purpose graphics processor coupled with the system interface. The general-purpose graphics processor comprises a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including a first command streamer, a second command streamer, and circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.

Abstract: Apparatus and method for concurrent performance monitoring. For example, one embodiment of an apparatus comprises: compute hardware logic to concurrently process a number of workloads, the compute hardware logic to be subdivided into a plurality of compute hardware contexts based on the number of workloads; and programmable performance monitoring circuitry to be dynamically partitioned to perform parallel performance monitoring operations to monitor performance of each of the plurality of compute hardware contexts while the number of workloads are concurrently processed, the programmable performance monitoring circuitry to differentiate between performance monitoring data of different compute hardware contexts based on a unique identifier associated with each of the compute hardware contexts.

Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

Abstract: Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.