Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Abstract: Compositions, methods, kits, and uses are provided for detecting or quantifying a Group A Streptococcus (GAS) nucleic acid, e.g., using nucleic acid amplification and hybridization assays.

Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

Abstract: Oligomer nucleotides, compositions, methods, kits, and uses are provided for detecting or quantifying a Human Cytomegalovirus virus 1 (CMV (human herpesvirus 5, HHV5) nucleic acid, e.g., using nucleic acid amplification and hybridization assays. Multiphase amplification of a CMV target sequence is also described. The oligomer nucleotides, compositions, methods, kits, and uses can be used to amplify and/or detect the UL56 gene of CMV.

Abstract: Disclosed are oligonucleotides, oligonucleotide compositions, kits, methods, formulations, and reaction mixtures that provide for sensitive and specific detection of a target nucleic acid sequence, or amplicon generated from a target nucleic acid sequence, of Varicella-Zoster Virus (VZV1 (if present) in a sample. The oligonucleotides, compositions, kits, methods, formulations, and reaction mixtures can be used to detect the presence of VZV in a sample. The oligonucleotides, compositions, kits, methods, formulations, and reaction mixtures can also be used to amplify specific target nucleic acid regions of VZV.

Abstract: Oligomer nucleotides, compositions, methods, kits, and uses are provided for detecting or quantifying a human polyomavirus BK virus (BKV) nucleic acid, e.g., using nucleic acid amplification and hybridization assays.

Abstract: Described herein is an accelerator device having a cache memory for which limits may be specified for a memory allocation according to a class of service associated with a thread, application, or virtual machine that created the memory allocation. The limits can include a specific set of enumerated cache ways that are designated as eligible to cache data for memory allocations associated with a class of service.

Abstract: Disclosed are compositions, methods, and kits that can be used to Epstein-Ban virus (EBV) in a sample undergoing testing. Nucleic acids of EBV can be isolated, amplified and detected with specificity by real-time PCR, and without interference from non-EBV organisms. In some embodiments, nucleic acids used for amplification are isolated from human blood, or blood products. Nucleic acid isolation, amplification and detection steps can all be carried out using an automated instrument.

Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to techniques for runtime flip stability characterization are described. In an embodiment, logic circuitry determines the amount of work to be performed by a processor to render a pattern during each of a plurality of Vertical blank (Vblank) intervals. Memory stores information corresponding to a workload to be executed by the processor during each of the plurality of Vblank intervals. An operating frequency of the processor may then be modified based at least in part on analysis of the stored information to indicate which of the plurality of Vblank intervals would provide an improved stability for rendering the pattern. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

Abstract: Method of preparing a biological sample appropriate for use in a subsequent in vitro nucleic acid amplification reaction. A biological sample is combined with an alkaline composition that lyses cells and denatures DNA to create a first liquid composition. The first liquid composition is then mixed with a buffer, a detergent, and a solid support that captures DNA to create a second liquid composition. The buffer, detergent, and solid support can be delivered as components of a single reagent. Captured DNA strands can be used as templates in subsequently performed nucleic acid amplification and detection reactions with improved sensitivity.

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.