Patents by Inventor Ankur Shah

Ankur Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210272349
    Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 2, 2021
    Applicant: Intel Corporation
    Inventors: TRAVIS SCHLUESSLER, ZACK WATERS, MICHAEL APODACA, DANIEL JOHNSTON, JASON SURPRISE, PRASOONKUMAR SURTI, SUBRAMANIAM MAIYURAN, PETER DOYLE, SAURABH SHARMA, ANKUR SHAH, MURALI RAMADOSS
  • Publication number: 20210269854
    Abstract: Method of preparing a biological sample appropriate for use in a subsequent in vitro nucleic acid amplification reaction. A biological sample is combined with an alkaline composition that lyses cells and denatures DNA to create a first liquid composition. The first liquid composition is then mixed with a buffer, a detergent, and a solid support that captures DNA to create a second liquid composition. The buffer, detergent, and solid support can be delivered as components of a single reagent. Captured DNA strands can be used as templates in subsequently performed nucleic acid amplification and detection reactions with improved sensitivity.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 2, 2021
    Inventors: Matthias JOST, Barbara L. EATON, Ankur SHAH
  • Publication number: 20210271539
    Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
    Type: Application
    Filed: February 9, 2021
    Publication date: September 2, 2021
    Inventors: Balaji VEMBU, Bryan WHITE, Ankur SHAH, Murali RAMADOSS, David PUFFER, Altug KOKER, Aditya NAVALE, Mahesh NATU
  • Publication number: 20210263853
    Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: ZACK S. WATERS, TRAVIS SCHLUESSLER, MICHAEL APODACA, ANKUR SHAH
  • Publication number: 20210263755
    Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.
    Type: Application
    Filed: November 30, 2018
    Publication date: August 26, 2021
    Inventors: Kun TIAN, Ankur SHAH, David COWPERTHWAITE, Zhi WANG, Zhenyu WANG, Kalyan KONDAPALLY, Jonathan BLOOMFIELD, Wei ZHANG
  • Publication number: 20210241418
    Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler
  • Publication number: 20210225061
    Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 22, 2021
    Applicant: Intel Corporation
    Inventors: Ankur Shah, Matthew Callaway, Vivek Garg, Rajeev K. Nalawadi, James Varga
  • Patent number: 10997086
    Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Aditya Navale, Ankur Shah, Murali Ramadoss, Ben Ashbaugh, Ronald Silvas
  • Patent number: 10997771
    Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Travis Schluessler, Zack Waters, Michael Apodaca, Daniel Johnston, Jason Surprise, Prasoonkumar Surti, Subramaniam Maiyuran, Peter Doyle, Saurabh Sharma, Ankur Shah, Murali Ramadoss
  • Patent number: 10997686
    Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler
  • Publication number: 20210096620
    Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Ankur Shah, Marc Beuchat
  • Patent number: 10937119
    Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Penne Lee, Ankur Shah, Ping Liu, Joseph Koston
  • Patent number: 10922161
    Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Bryan White, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Mahesh Natu
  • Patent number: 10909740
    Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Ankur Shah, Matthew Callaway, Vivek Garg, Rajeev K Nalawadi, James Varga
  • Publication number: 20200410627
    Abstract: Methods and apparatus relating to techniques for runtime flip stability characterization are described. In an embodiment, logic circuitry determines the amount of work to be performed by a processor to render a pattern during each of a plurality of Vertical blank (Vblank) intervals. Memory stores information corresponding to a workload to be executed by the processor during each of the plurality of Vblank intervals. An operating frequency of the processor may then be modified based at least in part on analysis of the stored information to indicate which of the plurality of Vblank intervals would provide an improved stability for rendering the pattern. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Ankur Shah, Marc Beuchat
  • Patent number: 10817433
    Abstract: Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Altug Koker, Ankur Shah, Murali Ramadoss, Niranjan Cooray
  • Publication number: 20200327636
    Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.
    Type: Application
    Filed: February 13, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: MURALI RAMADOSS, PENNE LEE, ANKUR SHAH, PING LIU, JOSEPH KOSTON
  • Patent number: 10796472
    Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Michael Apodaca, Ankur Shah, Ben Ashbaugh, Brandon Fliflet, Hema Nalluri, Pattabhiraman K, Peter Doyle, Joseph Koston, James Valerio, Murali Ramadoss, Altug Koker, Aditya Navale, Prasoonkumar Surti, Balaji Vembu
  • Publication number: 20200263242
    Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, Metapneumovirus, and/or Rhinovirus nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.
    Type: Application
    Filed: March 23, 2018
    Publication date: August 20, 2020
    Applicant: GEN-PROBE INCORPORATED
    Inventors: Mehrdad R. MAJLESSI, Ankur SHAH, Amber HILLIUS, Pamela DOUGLASS, Daniel KOLK
  • Publication number: 20200219223
    Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler