Abstract: In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.

Abstract: One embodiment provides a graphics processor including an active base die including a fabric interconnect and a chiplet including a switched fabric, wherein the chiplet couples with the active base die via an array of interconnect structures, the array of interconnect structures couple the fabric interconnect with the switched fabric, and the chiplet includes a first modular interconnect configured to couple a block of graphics processing resources to the switched fabric and a second modular interconnect configured to couple a memory subsystem with the switched fabric and the block of graphics processing resources, the memory interconnect including a set of memory controllers and a set of physical interfaces.

Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, Metapneumovirus, and/or Rhinovirus nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, Metapneumovirus, and/or Rhinovinis nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

Abstract: Security and support for trust domain operation is described. An example of a method includes processing, at an accelerator, one or more compute workloads received from a host system; upon receiving a notification that a trust domain has transitioned to a secure state, transition an original set of privileges for the accelerator to a downgraded set of privileges; upon receiving a command from the host system for the trust domain, processing the command in accordance with the trust domain; and upon receiving a request from the host system to access a register, for a register included in an allowed list of registers for access, allow access to the register, and, for a register that is not within the allowed list of registers for access, disallowing access to the register.

Abstract: The disclosed disclosure is related to methods, compositions, and kits for targeting Adenovirus, nucleic acid. Compositions include amplification oligomers and/or detection probe oligomers. Kits and methods comprise at least one of these oligomers. Methods include uniplex and multiplex amplification and detection reactions.

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.

Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.