Patents by Inventor Anna W. Topol
Anna W. Topol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8241995Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.Type: GrantFiled: September 18, 2006Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, Cornelia K. Tsang
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Publication number: 20120158882Abstract: Embodiments of the disclosure relate to storing and sharing data in a scalable distributed storing system using parallel file systems. An exemplary embodiment may comprise a network, a storage node coupled to the network for storing data, a plurality of application nodes in device and system modalities coupled to the network, and a parallel file structure disposed across the storage node and the application nodes to allow data storage, access and sharing through the parallel file structure. Other embodiments may comprise interface nodes for accessing data through various file access protocols, a storage management node for managing and archiving data, and a system management node for managing nodes in the system.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sven Oehme, Marc Thadeus Roskow, Stephen Leonard Schwartz, Anna W. Topol, Daniel James Winarski
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Publication number: 20120147738Abstract: A node communicates with a first network through a link aggregation of at least one primary port and at least one backup port. The link aggregation is for rerouting a communication with the first network to occur through the backup port in response to a malfunction in the communication through the primary port. In response to a malfunction in the communication through the backup port, the node communicates with a second network.Type: ApplicationFiled: December 9, 2010Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Alexander Abderrazag, Susan K. Schreitmueller, Anna W. Topol
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Publication number: 20120143828Abstract: A processor-implemented method, system and/or computer program product for managing computer file storage is presented. A file, which is designated for storage, is received. Upon determining that the file exceeds a pre-determined size, the file is stored in a pre-designated folder that is reserved for oversized files. This pre-designated folder is protected such that any file stored within the pre-designated folder is prevented from being moved into archival storage.Type: ApplicationFiled: February 8, 2012Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MARY P. KUSKO, FRANK E. LEVINE, STELLA L. TAYLOR, ANNA W. TOPOL
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Patent number: 8176105Abstract: A computer-implemented method, system and computer program product for managing computer file storage is presented. In one embodiment the method includes receiving a file for storage. In response to determining that the file exceeds a pre-determined size, the file is stored in a pre-designated folder that is reserved for oversized files.Type: GrantFiled: December 8, 2008Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Mary P. Kusko, Frank E. Levine, Stella L. Taylor, Anna W. Topol
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Publication number: 20110282844Abstract: A system, method and computer program product for archiving image, audio, and text data with metadata encapsulation in a client-server storage library is described. The server receives and holds the images, audio, or text to be archived in an image, audio or text logical partition which includes a directory of the images, audio, or text. The information is encapsulated in a metadata wrapper and stored in the library as a closed image, audio, or text file along with a closed copy of the directory. The closed image, audio, or text directory is also stored in the client. The images may be encapsulated in MXF, DICOM, Tape Archive (TAR) or GZIP formats. The storage library may have magnetic tapes, magnetic disks or optical disks as storage media.Type: ApplicationFiled: May 17, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Allen Keith Bates, Louie Arthur Dickens, Timothy A. Johnson, Craig Anthony Klein, Yun Mou, Stephen Leonard Schwartz, Anna W. Topol, Daniel James Winarski
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Publication number: 20110076670Abstract: A first set of antibodies are bonded to a substrate, and are exposed to and bonded with target antigens. A second set of antibodies are bonded to nanoparticles, and the nanoparticle labeled antibodies are exposed to the targeted antigens. An electromagnetic write-head magnetizes the nanoparticles, and then a read-sensor detects the freshly magnetized nanoparticles. The substrate comprises a flexible film or a Peltier material to allow selective heating and cooling of the antigens and antibodies. Nanoparticles of different magnetic properties may be selectively paired with antibodies associated with different antigens to allow different antigens to be detected upon a single scan by the read-sensor.Type: ApplicationFiled: September 22, 2010Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dylan Joseph Boday, Lee Curtis Randall, Stephen Leonard Schwartz, Anna W. Topol, Daniel James Winarski
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Publication number: 20110077902Abstract: A circuit for controlling an electromagnetic head module to detect antigens on a biosample track comprising a processor for receiving position-error-servo signal from the PES read sensor, a write head for magnetizing nanoparticles attached to antigens, and a read sensor for detecting the nanoparticle-labeled antigens. The circuit may further comprise an X-axis actuator for controlling the head module in the direction perpendicular to the track and an Y-axis actuator coupled to the head module and the X-axis actuator for controlling the head module in the direction of the track. Target antigens are attached to the biosample track and nanoparticles via antibodies.Type: ApplicationFiled: September 22, 2010Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tara L. Awezec, Dylan Joseph Boday, Stephen Leonard Schwartz, Anna W. Topol, Daniel James Winarski
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Publication number: 20110077869Abstract: A circuit for detecting antigens on biosample tracks comprising a processor, an electromagnetic write head for magnetizing nanoparticles attached to the antigens via antibodies in response to a write signal from the processor, and a first amplifier for supplying power to the write head. The circuit further comprises a magneto-resistive read sensor for detecting the magnetized nanoparticles upon receiving a read signal from the processor, and a second amplifier for supplying power to the read sensor. The write head and read sensor may be part of a head module in a magnetic tape drive. Nanoparticles of differing magnetic properties may be selectively paired with antibodies associated with different antigens to allow different antigens to be detected upon a single scan by the read-sensor.Type: ApplicationFiled: September 22, 2010Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dylan Joseph Boday, Louie Arthur Dickens, Steven Mark Groff, Icko Eric Timothy Iben, Wayne Alan McKinley, Lee Curtis Randall, Stephen Leonard Schwartz, Anna W. Topol, Daniel James Winarski
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Publication number: 20110076782Abstract: Embodiments of the invention relate to magnetizing and detecting nanoparticle-labeled antigens on biosample tracks deposited on a tape media. An aspect of the invention comprises apparatus and methods for labeling antigens with demagnetized nanoparticles, magnetizing the nanoparticles with an electromagnetic write head, and detecting the antigens via the magnetized nanoparticles by reading the tape media with a read sensor in a read-after-write operation. The write head and read sensor are part of a head-module of magnetic tape drive. Target antigens are attached to the biosample tracks by antibodies. Nanoparticles of differing magnetic properties may be selectively paired with antibodies associated with different antigens to allow multiple antigens to be detected upon a single scan by the read sensor.Type: ApplicationFiled: September 22, 2010Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tara L. Awezec, Dylan Joseph Boday, Lee Curtis Randall, Stephen Leonard Schwartz, Anna W. Topol, Daniel James Winarski
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Patent number: 7875528Abstract: A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.Type: GrantFiled: February 7, 2007Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Douglas C. La Tulipe, Jr., Steven E. Steen, Anna W. Topol
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Patent number: 7847357Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.Type: GrantFiled: September 9, 2009Date of Patent: December 7, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Thomas W. Dyer, David R. Medeiros, Anna W. Topol
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Publication number: 20100255262Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.Type: ApplicationFiled: September 18, 2006Publication date: October 7, 2010Inventors: Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, Cornelia K. Tsang
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Patent number: 7786596Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.Type: GrantFiled: February 27, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, Albert M. Young
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Publication number: 20100211950Abstract: The illustrative embodiments disclose a computer implemented method, apparatus, and computer program product for managing a set of applications. In one embodiment, the process registers a system management event in an application configuration database. Responsive to detecting the registered system management event during execution of one application of the set of applications, the process identifies applications of the set of applications associated with the registered system management event that are executing. The process then terminates the applications of the set of applications associated with the registered system management event that are executing. Responsive to terminating the applications of the set of applications associated with the registered system managing event that are executing, the process then executes a handler that processes the registered system management event.Type: ApplicationFiled: February 19, 2009Publication date: August 19, 2010Applicant: International Business Machines CorporationInventors: Mary P. Kusko, Frank Eliot Levine, Stella Lee Taylor, Anna W. Topol
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Publication number: 20100146019Abstract: A computer-implemented method, system and computer program product for managing computer file storage is presented. In one embodiment the method includes receiving a file for storage. In response to determining that the file exceeds a pre-determined size, the file is stored in a pre-designated folder that is reserved for oversized files.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary P. Kusko, Frank E. Levine, Stella L. Taylor, Anna W. Topol
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Publication number: 20100133616Abstract: Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.Type: ApplicationFiled: February 8, 2010Publication date: June 3, 2010Inventors: David J. Frank, Douglas C. La Tulipe, JR., Steven E. Steen, Anna W. Topol
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Patent number: 7683478Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.Type: GrantFiled: February 6, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, Albert M. Young
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Patent number: 7666723Abstract: Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.Type: GrantFiled: February 22, 2007Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: David J. Frank, Douglas C. La Tulipe, Jr., Steven E. Steen, Anna W. Topol
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Publication number: 20090321847Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.Type: ApplicationFiled: September 9, 2009Publication date: December 31, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Thomas W. Dyer, David R. Medeiros, Anna W. Topol