Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract: Systems and methods are provided for obtaining and using nonvolatile memory (“NVM”) health information. Health information can include a variety of information associated with the performance and reliability of portions of an NVM device, such as the number of errors detected in a portion of NVM or the amount of time required to read from or program a portion of nonvolatile memory. During operation, address specific health information may be stored passively on a host device and provided as part of a command to a memory controller. The memory controller may extract the health information from the command and use the information to execute access requests. After an access request is completed, the memory controller can update the health information and transmit the information back to the host device.

Abstract: In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.

Abstract: In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host.

Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Abstract: An ad-hoc cash-dispensing network that allows users to efficiently exchange cash is provided. The ad-hoc cash-dispensing network includes a cash-dispensing server, a network, and a plurality of client terminals that connect to the cash-dispending server through the network. The user of a client terminal sends a request for cash to the cash-dispensing server. The request for cash includes the location of the client terminal. Based on this location, the cash-dispensing server locates one or more other users that are close/proximate to the requesting user and verifies that at least one of these proximate users is willing and able to provide the requested amount of cash. Following the transfer of cash between the parties, the requesting user's account is charged for the service while the providing user's account is credited for the service.

Abstract: In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Abstract: In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus.

Abstract: In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, one or more trim values from the host device, wherein the trim values define one or more parameters for accessing the non-volatile memory, and the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the trim values from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained by providing commands to the memory device.

Abstract: In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device.

Abstract: Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Abstract: Stacked die having vertically-aligned conductors and methods for making the same are disclosed for providing a non-volatile memory, such as flash memory (e.g., NAND flash memory), for use in an electronic device.

Abstract: In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at a time when the data was written to the non-volatile memory cells. The method can further include reading, by the memory device, the data from the non-volatile memory cells. The method can also include processing the read data based on, at least, the retrieved temperature information; and providing the processed data.

Abstract: This document generally describes systems, devices, methods, and techniques for variably controlling impedance for a memory device where multiple NVM units (e.g., NVM dies) are accessible over a shared bus. Impedance can be varied using switches that are configured to switch between a NVM unit and an impedance terminal. Switches can be adjusted during operation of a memory device so that a memory controller is connected over a shared bus to a selected single NVM unit and one or more impedance terminals. Impedance terminals can be configured to provide a relatively small load (a smaller load than an NVM unit) that is impedance matched (alone or in combination with other impedance terminals and/or a NVM unit) with a source impedance on a shared bus that is provided by a memory controller.

Abstract: This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.

Abstract: Stacked die having vertically-aligned conductors and methods for making the same are disclosed for providing a non-volatile memory, such as flash memory (e.g., NAND flash memory), for use in an electronic device.

Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

Abstract: Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.