Patents by Inventor Anthony J. Annunziata

Anthony J. Annunziata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011698
    Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
  • Publication number: 20200403151
    Abstract: A spin-transfer torque magneto-resistive random access memory (STT-MRAM) device is provided. The STT-MRAM device includes a substrate, a dielectric layer and a magnetic tunnel junction (MTJ) stack. The substrate includes a conductor and a landing pad. The MTJ stack includes a reference layer element, a free layer assembly and a barrier layer element. The reference layer element is lined with redeposited metal and is disposed on the landing pad within the dielectric layer. The free layer assembly includes a free layer element, a hard mask layer element disposed on the free layer element, redeposited metal lining sidewalls of the free and hard mask layer elements and dielectric material lining the redeposited metal. The barrier layer element is interposed between and has a same width as the reference layer element and the free layer assembly.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 24, 2020
    Inventors: Anthony J. Annunziata, Bruce B. Doris, Eugene J. O'Sullivan
  • Publication number: 20200266342
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Applicant: International Business Machines Corporation
    Inventors: Anthony J. ANNUNZIATA, Chandrasekara KOTHANDARAMAN, Nathan P. MARCHACK, Eugene J. O'SULLIVAN
  • Patent number: 10741752
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekharan Kothandaraman, John R. Sporre
  • Patent number: 10734571
    Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Joel D. Chudow, Daniel C. Worledge
  • Patent number: 10700263
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate. At least one trench line is formed within the substrate. A pad layer is formed in contact with the at least one trench line. A seed layer is formed on and in contact with the pad layer. The seed layer has a Root Mean Square surface roughness equal to or less than 3 Angstroms. A magnetic tunnel junction stack is formed on and in contact with the seed layer. The method includes forming a seed layer on and in contact with a semiconductor structure. The seed layer is annealed and then planarized. A magnetic tunnel junction stack is formed on and in contact with the seed layer after the seed layer has been planarized.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Janusz J. Nowak, Eugene J. O'Sullivan
  • Publication number: 20200144495
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekharan Kothandaraman, John R. Sporre
  • Patent number: 10644232
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Eugene J. O'Sullivan
  • Patent number: 10622553
    Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Hiroyuki Miyazoe
  • Patent number: 10586921
    Abstract: A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Daniel C. Edelstein, Eugene J. O'Sullivan, Henry K. Utomo
  • Patent number: 10586920
    Abstract: A semiconductor structure is disclosed herein. The semiconductor structure includes two or more pillar structures disposed over a top surface of a substrate. The semiconductor structure further includes two or more contacts to the two or more pillar structures. The semiconductor structure further includes an insulator disposed between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Daniel C. Edelstein, Eugene J. O'Sullivan, Henry K. Utomo
  • Patent number: 10566524
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekara Kothandaraman, John R. Sporre
  • Patent number: 10497862
    Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
  • Publication number: 20190288191
    Abstract: A method of fabricating a magneto-resistive random access memory (MRAM) cell with at least one magnetic tunnel junction (MTJ) is provided. The method includes disposing a metallic landing pad within a dielectric pad in a substrate and selectively depositing seed layer material over the substrate. This selective deposition forms a seed layer on which the MTJ is disposable on the metallic landing pad but not the dielectric pad.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Inventors: ANTHONY J. ANNUNZIATA, CHANDRASEKHARAN KOTHANDARAMAN, NATHAN P. MARCHACK, EUGENE J. O'SULLIVAN
  • Patent number: 10388857
    Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Armand A. Galan, Steve Holmes, Eric A. Joseph, Gen P. Lauer, Qinghuang Lin, Nathan P. Marchack
  • Patent number: 10374152
    Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junctions serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that when the second field effect transistor of a selected magnetic tunnel junction is switched to direct the programming voltage to program the selected magnetic tunnel junction an unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, John K. DeBrosse, Chandrasekharan Kothandaraman
  • Publication number: 20190237659
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate. At least one trench line is formed within the substrate. A pad layer is formed in contact with the at least one trench line. A seed layer is formed on and in contact with the pad layer. The seed layer has a Root Mean Square surface roughness equal to or less than 3 Angstroms. A magnetic tunnel junction stack is formed on and in contact with the seed layer. The method includes forming a seed layer on and in contact with a semiconductor structure. The seed layer is annealed and then planarized. A magnetic tunnel junction stack is formed on and in contact with the seed layer after the seed layer has been planarized.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: Anthony J. ANNUNZIATA, Chandrasekharan KOTHANDARAMAN, Janusz J. NOWAK, Eugene J. O'SULLIVAN
  • Patent number: 10355204
    Abstract: A method of fabricating a magneto-resistive random access memory (MRAM) cell with at least one magnetic tunnel junction (MTJ) is provided. The method includes disposing a metallic landing pad within a dielectric pad in a substrate and selectively depositing seed layer material over the substrate. This selective deposition forms a seed layer on which the MTJ is disposable on the metallic landing pad but not the dielectric pad.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Eugene J. O'Sullivan
  • Publication number: 20190207099
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Anthony J. ANNUNZIATA, Chandrasekharan KOTHANDARAMAN, Nathan P. MARCHACK, Eugene J. O'SULLIVAN
  • Publication number: 20190115528
    Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Hiroyuki Miyazoe