Abstract: Applicators for a microprojection array and methods of using the applicators are described.

Abstract: Applicators for a microprojection array capable of multiple impacts and methods of using the applicators are described.

Abstract: Methods and materials relate to degradable detergents. The degradable detergents have degradable linkages that are cleaved when subjected to elevated temperature and/or reduced pressure. The detergents are compatible with spectrometric analysis, such as mass spectrometry. The surfactant comprises at least one fluorinated alkyl moiety and at least one cleavable moiety, wherein the surfactant degrades into a plurality of volatile degradation products when injected into a mass spectrometer.

Abstract: Method and apparatus for cooling a heated mould (12, 14, 16) of a device (10) for blow-moulding thermoplastic containers, the device including: a mould (12, 14, 16) having an internal face which delimits a moulding cavity (18) and which includes an external face (20, 28) which surrounds the moulding cavity (18); heating elements for heating the mould to a determined temperature and which are deactivated when the cooling method is implemented; characterized in that the mould (12, 14, 16) is cooled by circulating heat-transfer fluid directly in contact with the external face (20, 28) thereof.

Abstract: A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component where data is accessed on leading and falling edges of a clock signal.

Abstract: The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.

Abstract: A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.

Abstract: An applicator for a microprojection array is described. In one embodiment, the applicator comprises an energy-storing element. Application of force causes the compressed energy-storing element to extend or transition from first and second configurations, releasing stored energy to deploy a holding member in the application which is configured to hold an array of microprojections. In another embodiment, the applicator comprises an energy storing element with two stable configurations, a first stable configuration and second stable configuration. Application of force causes the energy-storing element to transition from the higher energy first stable configuration to the lower energy second stable configuration, releasing the difference in energies of the two states to deploy a holding member in the application which is configured to hold an array of microprojections.

Abstract: The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.

Abstract: Systems and methods of detecting an auto-boot mode and booting data from a serial peripheral interface to a processor without the need of a read instruction utilizing a serial peripheral interface having an auto-boot mode detector are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to serially communicate data between the processor and at least two peripherals, and an auto-boot component operably coupled to the serial processing component, comprising an auto-boot mode detector configured to determine whether a boot mode exists based on detecting whether serial input data is received during a predetermined wait state, and configured to selectively boot data to a start address associated with the processor based on the boot mode determination.

Abstract: Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.

Abstract: The present invention provides liquid chromatography-mass spectrometry methods and kits for the specific, sensitive and rapid detection as well as quantitation of free amino acids in samples following High Pressure Liquid Chromatography (HPLC) separation.

Abstract: Method for radiographic imaging, in particular for measuring the bone mineral density of an osseous body, this method involving an operation which consists in determining the value of a composite index using, on the one hand, digitized radiological data, and, on the other hand, a three-dimensional generic model of said osseous body.

Abstract: Method for correcting an acquired medical image of a patient showing a representation of an internal body structure, the acquired image having been acquired in a medical imager having a radiation source and a radiation detector spaced from one another along an image-taking direction, and between which the patient is disposed. One obtains, from the acquired image, a corrected image taking into account a position of the internal body structure along the image-taking direction.

Abstract: Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.

Abstract: Systems and methods of detecting an auto-boot mode and booting data from a serial peripheral interface to a processor without the need of a read instruction utilizing a serial peripheral interface having an auto-boot mode detector are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to serially communicate data between the processor and at least two peripherals, and an auto-boot component operably coupled to the serial processing component, comprising an auto-boot mode detector configured to determine whether a boot mode exists based on detecting whether serial input data is received during a predetermined wait state, and configured to selectively boot data to a start address associated with the processor based on the boot mode determination.

Abstract: Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.

Abstract: Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.

Abstract: Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.

Abstract: A behind-the-ear hearing aid including an arcuate, integrally-molded instrument case adapted for residing behind an ear of a wearer. The instrument case defines a substantially seamless electronics compartment containing a microphone and a loudspeaker operatively connected to the microphone. An amplifier serves to boost a sound signal transmitted from the microphone through the loudspeaker to the ear of the wearer.