Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: Solid pigment preparations comprising as essential constituents (A) from 60% to 95% by weight of at least one pigment, (B) from 2.5% to 35% by weight of at least one water-soluble surface-active additive based on polyurethanes and (C) from 2.5% to 35% by weight of at least one nonionic water-soluble surface-active additive (C1) based on polyethers and/or of an anionic water-soluble additive other than additives (B) which is based on polymers of ethylenically unsaturated carboxylic acids (C2), and also production and use of the pigment preparations for coloration of macromolecular organic and inorganic materials and also of plastics.

Abstract: The damaged headlight, fog light or tail light mounting tab is repaired by cutting away all of the old damaged mount tab. The new mounting tab is bent and trimmed to mirror the old mount tab, then is screwed or glued down to the housing in replace of the old damaged mounting tab.

Abstract: The present invention relates to industrial bitumen compositions comprising at least one industrial bitumen, and at least one surface-active agent for reducing the viscosity of said bitumen. The present invention also relates to the use of said industrial bitumen compositions for the preparation of industrial bitumen-containing products, as well as the products thus obtained.

Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.

Abstract: A system includes a capacitor, a plurality of notification devices connected in parallel with the capacitor, and a controller. The controller is capable of determining capacitance of the capacitor during charge-up of the capacitor, and the controller is capable of determining the wiring impedance of the emergency notification circuit during discharge of the capacitor.

Abstract: The invention relates to a bituminous composition containing at least one bitumen and at least one polyolefin capable of forming a supramolecular assembly comprising one or more associative group(s). The invention also relates to the use of such bituminous composition for the preparation of asphalt mixtures useful for the coating of rolling surfaces, for the preparation of water-proofing coatings, and for the preparation of adhesive formulations.

Abstract: The present invention relates to a method of improving the incorporation of recycled bituminous products by using at least one surfactant as an alternative to the known rejuvenating oils, for the preparation of asphalt mixes containing recycled bituminous products. The use of such alternative surfactant(s) results in better mechanical properties of the asphalt mix, while using smaller amounts of fresh bitumen and greater amounts of recycled bituminous products.

Abstract: Fiber optic modules having pigtails and related strain relief constructions for the fiber optic harness are disclosed. The fiber optic module assembly has a fiber pigtail exiting module, the assembly includes a main body of the module defining an internal chamber disposed between a first side and a second side, a plurality of fiber optic components disposed at the first side of the module, and a fiber optic harness including the fiber pigtail. The fiber optic harness includes a plurality of optical fibers within a portion of a protective tube on the pigtail portion and a strain-relief assembly for inhibiting movement between the optical fibers and protective tube. Consequently, the strain-relief assembly secures the plurality of optical fibers and the protective tube to the main body of the module.

Abstract: According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation.

Abstract: High-density fiber optic modules and fiber optic module housings and related equipment are disclosed. In certain embodiments, a front opening of a fiber optic module and/or fiber optic module housing is configured to receive fiber optic components. The width and/or height of the front opening can be provided according to a designed relationship to a width and/or height, respectively, of a front side of a main body of the fiber optic module and/or fiber optic module housing. In this manner, a high density of fiber optic components and/or connections for a given space of the front side of the fiber optic module can be supported by the fiber optic module and/or fiber optic module housing. The fiber optic modules and fiber optic module housings disclosed herein can be disposed in fiber optic equipment including but not limited to a fiber optic chassis and a fiber optic equipment drawer.

Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Abstract: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.