Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

Abstract: Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.

Abstract: Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative bias temperature instability (NBTI) or oxide degradation on the register. Other embodiments are also described.

Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Abstract: Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.

Abstract: The present invention relates to bitumen additive mixtures, their use and application for the fabrication of asphalt mixtures used in pavement and waterproofing, and more specifically for construction, repair and maintenance of sidewalks, roads, highways, parking lots or airport runaways and service roads and any other rolling surfaces.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.

Abstract: A system includes a capacitor, a plurality of notification devices connected in parallel with the capacitor, and a controller. The controller is capable of determining capacitance of the capacitor during charge-up of the capacitor, and the controller is capable of determining the wiring impedance of the emergency notification circuit during discharge of the capacitor.

Abstract: Embodiments disclosed herein include ferrule assembly having a ferrule and a ferrule boot that is coupled to the ferrule. The ferrule boot is used for aligning an array of optical fibers in the desired arrangement when entering the ferrule. In one embodiment, the ferrule boot may have a two-piece construction that includes a fiber alignment portion that defines a first groove for a first row of optical fibers and a cover portion. Moreover, the ferrule boot may be configured to accommodate multiple rows of optical fibers. Other embodiments may use a bendable material for the ferrule boot and/or include color coding for aiding the craft with fiber positioning.

Abstract: A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

Abstract: The present invention generally relates to compositions and methods for determining kinase activity. In some cases, the compositions comprise a triazole heterocycle. In some embodiments, the compositions comprise a quinoline moiety. In one aspect, the present invention is directed to compositions that undergo chelation-enhanced fluorescence (CHEF). In some cases, the compositions may have fluorescence emission spectra with peak maxima greater than 490 nm. The compositions of the present invention can be used, in certain embodiments, to detect phosphorylated substrates and biological processes such as phosphorylation events.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.

Abstract: The invention relates to a bituminous composition containing at least one bitumen and at least one polyolefin capable of forming a supramolecular assembly comprising one or more associative group(s). The invention also relates to the use of such bituminous composition for the preparation of asphalt mixtures useful for the coating of rolling surfaces, for the preparation of water-proofing coatings, and for the preparation of adhesive formulations.

Abstract: The present invention relates to a bituminous composition comprising at least one bitumen and at least one polycondensate capable of forming a supramolecular assembly comprising one or more associative group(s). The present invention also relates to the use of such bituminous composition for the preparation of asphalt mixtures useful for the coating of rolling surfaces, for the preparation of water-proofing coatings, and the for the preparation of adhesive formulations.

Abstract: A process for preparing a zeolite-based monolith including dry-mixing zeolite particles and a temporary binder until homogenization; adding silica and water dispersion; wet-kneading and high-shear mixing until obtaining a homogenous pulp; extrusion-molding the pulp resulting from the previous step; controlled drying of the mold obtained; and oxidizing at a high temperature to obtain the monolith.