Abstract: Solar tracker (1) for the orientation of solar panels (2), which is supported on a base (3) and comprises a holding structure (4) for the solar panels (2). It comprises an intermediate support element (5) to which the holding structure (4) of the panels (2) is articulated. The two movements of the holding structure (4) of the panels (2) are respectively produced by: a) a first mechanism that produces a flat movement, with three mobile rigid elements—one central (6) and two lateral (7). The rigid lateral elements (7) can be moved by means of linear actuators (10). The intermediate support element (5) can be on one of the mobile rigid elements (6, 7) or be coincident with it, and b) a second mechanism that acts on the holding structure (4) and is located on the intermediate support element (5); it comprises means to make the holding structure (4) rotate around an axis integral with the intermediate support element (5).

Abstract: Techniques for achieving coherence between dynamically optimized code and original code are disclosed. In an embodiment, a search is performed for a first entry for a first page containing a first code region in a first data structure. The first code is used to determine whether a first indicator in the first entry is set to a first value. The first entry is added to the first data structure, in response to failing to find the first entry in the first data structure. A second search may be performed for a second entry for the first code region in a second data structure, in response to determining that the first indicator is set to the first value. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Abstract: Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of a precomputation slice and are stored in a validation buffer for later validation. A global register file holds the committed architecture state generated by a non-speculative thread. Each thread unit includes a local register file. A directory indicates, for each architectural register, which speculative thread(s) have generated a value for the architectural register. Other embodiments are also described and claimed.

Abstract: The present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynamically estimating a remaining lifetime of the device based on the dynamic usage. Depending on the estimated remaining lifetime, the device may be controlled in a desired manner.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: The present invention relates to a bituminous composition comprising at least one bitumen and at least one polycondensate capable of forming a supramolecular assembly comprising one or more associative group(s) The present invention also relates to the use of such bituminous composition for the preparation of asphalt mixtures useful for the coating of rolling surfaces, for the preparation of water-proofing coatings, and the for the preparation of adhesive formulations.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: The present invention relates to a bituminous composition comprising at least one bitumen and at least one polycondensate capable of forming a supramolecular assembly comprising one or more associative group(s). The present invention also relates to the use of such bituminous composition for the preparation of asphalt mixtures useful for the coating of rolling surfaces, for the preparation of water-proofing coatings, and the for the preparation of adhesive formulations.

Abstract: In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.

Abstract: A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

Abstract: This invention relates to the modification of bitumen by polymeric materials used particularly for the preparation of asphalt mixtures with enhanced mechanical properties, wherein the polymeric materials are selected from additives capable of forming a supramolecular assembly. The modified bitumen may be used for the fabrication of asphalts mixtures with mineral aggregates used in construction or maintenance of sidewalks, roads, highways, parking lots or airport runaways and service roads and any other rolling surfaces.

Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Abstract: A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

Abstract: A method to process grease trap waste or refuse and remove organic matter, and reclaim fats, oils, and grease (FOG) found in it. The process is initiated after dewatering the grease trap material to increase its concentration; the resulting sludge is then mixed with a solvent. The dissolved fractions of fats, oils, and grease are separated using mechanical methods. The solids are washed to further remove any traces of fats, oils, and grease. The solids, substantially free from organic content, are dried to remove any water and/or organic matter remaining, rendering inert solids that can be safely disposed of according to Environmental Protection Agency (EPA) regulations. All fats, oils, and, grease fractions are separated, containing no inert materials, and no water. The solvent is recuperated (recycled), allowing it to be used over again. The recuperated grease fractions, highly pure and homogeneous, constitute an excellent raw material for further oleo-chemical processes and applications.

Abstract: The invention relates to a method including spraying steam in the form of multiple jets with a pressure and a temperature depending on the characteristics of the solar panel to be cleaned and of the impurities to be removed and at an angle that can be adjusted relative to the panel. The method can be combined with gentle cleaning using elements contacting the surface of the panels to be cleaned. The device includes a self-propelled vehicle, a water tank feeding a system for treating and purifying the water prior to feeding a steam generator, with a means for regulating the output temperature and pressure of the steam, which enters a system for distribution to the steam diffusers, which are coupled on a support associated with a cantilevered structure of the self-propelled vehicle.

Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.