Abstract: A solution for regulating a voltage for a broad range of integrated circuits (ICs) using a plurality of switch capacitor voltage regulator circuits is disclosed. A system can include a plurality of circuits configured to provide a voltage output responsive to a voltage input. Each circuit can include a plurality of switches and one or more capacitors and can be coupled in parallel with each of other circuits of the plurality of circuits, so that an input of each circuit is coupled to the voltage input and an output of each circuit is coupled to the voltage output. The plurality of switches of each circuit can be configured to switch on and off at a phase that is different from a phase of at least one another plurality of switches of another circuit of the plurality of circuits.

Abstract: The subject technology is directed to systems and methods for semiconductor devices with extended high-bandwidth memory (HBM) offsets. In a specific embodiment, the subject technology provides an apparatus that includes a circuit comprising a first connector and a second connector. The circuit is configured to send a first signal using the first connector to indicate a first selection. The apparatus further includes a first memory device comprising a first selector and a third connector and a fourth connector. The first selector is configured to couple the third connector to the second connector based on the first signal. The one or more connectors of the first memory devices cover a broad distance to ensure robust connectivity between the circuit and the first memory device. There are other embodiments as well.

Abstract: A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.

Abstract: The present invention relates to a method of producing a direct compression tablet composition comprising the step of processing ibuprofen, a hydrophilic polymer, and an inorganic excipient by an extrusion process to produce an extruded composition in which the ibuprofen forms a solid dispersion/solution within the hydrophilic polymer. The invention is particularly useful in preparing oral dissolvable tablets. Also provided are composition comprising an inorganic excipient and ibuprofen within a hydrophilic polymer.

Abstract: A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.

Abstract: An electrical device for transporting electrical signals, wherein the electrical device comprises a plurality of signal wires each configured for transporting electrical signals, and a plurality of shield wires being staggered with respect to each other and each being configured for shielding signal wires with respect to each other, wherein each shield wire is arranged between a respective pair of signal wires and extends only along a subsection of each signal wire of the respective pair.

Abstract: A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.

Abstract: A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.

Abstract: A method of producing an extruded, powdered/granulated composition comprising an active pharmaceutical ingredient (API), by the steps of providing an API and a porous inorganic excipient, and processing them by an extrusion process to directly produce an extruded, powdered/granulated composition wherein the API is at least partially absorbed within the pores of the inorganic excipient. In preferred embodiments, the API is melted, or solubilised in a solubilizer.

Abstract: The invention relates to a process of preparing a salt of an active pharmaceutical ingredient, the process comprising providing a blend of an active pharmaceutical ingredient and a salt forming substance, mixing the blend, optionally in the presence of added water, to react the active pharmaceutical ingredient with the salt forming substance to provide the salt of the active pharmaceutical ingredient; wherein when the active pharmaceutical ingredient is acidic, the salt forming substance is a base and the pKa difference between the acidic active pharmaceutical ingredient and the base is greater than 1, typically greater than 2 or preferably greater than 3; or when the active pharmaceutical ingredient is basic, the salt forming substance is an acid and the pKa difference between the basic active pharmaceutical ingredient and the acid is greater than 1, typically greater than 2 or preferably greater than 3.

Abstract: The invention relates to a process of preparing a salt of an active pharmaceutical ingredient, the process comprising providing a blend of an active pharmaceutical ingredient and a salt forming substance, mixing the blend, optionally in the presence of added water, to react the active pharmaceutical ingredient with the salt forming substance to provide the salt of the active pharmaceutical ingredient; wherein when the active pharmaceutical ingredient is acidic, the salt forming substance is a base and the pKa difference between the acidic active pharmaceutical ingredient and the base is greater than 1, typically greater than 2 or preferably greater than 3; or when the active pharmaceutical ingredient is basic, the salt forming substance is an acid and the pKa difference between the basic active pharmaceutical ingredient and the acid is greater than 1, typically greater than 2 or preferably greater than 3,

Abstract: The present invention relates to a method of producing a direct compression tablet composition comprising the step of processing ibuprofen, a hydrophilic polymer, and an inorganic excipient by an extrusion process to produce an extruded composition in which the ibuprofen forms a solid dispersion/solution within the hydrophilic polymer. The invention is particularly useful in preparing oral dissolvable tablets. Also provided are composition comprising an inorganic excipient and ibuprofen within a hydrophilic polymer.

Abstract: A method of producing an extruded, powdered/granulated composition comprising an active pharmaceutical ingredient (API), by the steps of providing an API and a porous inorganic excipient, and processing them by an extrusion process to directly produce an extruded, powdered/granulated composition wherein the API is at least partially absorbed within the pores of the inorganic excipient. In preferred embodiments, the API is melted, or solubilised in a solubilizer.

Abstract: A die having multiple sets of contact pads, with each such set having two or more contact pads distributed over the die and electrically interconnected using a respective electrical intra-die path to enable die reuse in a manner that causes electrical inter-die buses to be relatively short in length. Each electrical intra-die path can optionally include one or more respective buffer circuits configured to reduce degradation of the various signals that are being shared by the reused dies. In some embodiments, multiple reused dies can be arranged in a linear or two-dimensional array on an interposer or on the package substrate and packaged together with one or more non-reused dies in a single integrated-circuit package.

Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.

Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.

Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.

Abstract: An integrated circuit includes a number of probe pads arranged in a staggered manner in a core region of the integrated circuit and a number of bond pads in an Input/Output (I/O) region surrounding the core region. The core region includes logic circuitry therein, and the I/O region is configured to enable the core region to communicate with one or more external circuit(s) through the number of bond pads. The integrated circuit also includes a die metal interconnect separating a bond pad area in the I/O region from a probe pad area in the core region. A dimension of the die metal interconnect and/or a position of the die metal interconnect between the probe pad area and the bond pad area is variable.

Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.

Abstract: Disclosed are a system and method of separate probe and bond regions of an integrated circuit (IC). An IC, an I/O region adjacent to the core region to enable the core region, and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area outside the I/O region of the IC are disclosed. The die metal interconnect may have a length that is greater than the bond pad area length and/or the probe pad area length, and a width that is less than the bond pad area width and/or the probe pad area width. An in-front staggering technique may be used at a die corner of the IC to maintain the bond pad area in the I/O region, and a side staggering technique may be used at the die corner of the IC to maintain the bond pad area in the I/O region.