Patents by Inventor Anwar Ali

Anwar Ali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190022010
    Abstract: The invention relates to a process of preparing a salt of an active pharmaceutical ingredient, the process comprising providing a blend of an active pharmaceutical ingredient and a salt forming substance, mixing the blend, optionally in the presence of added water, to react the active pharmaceutical ingredient with the salt forming substance to provide the salt of the active pharmaceutical ingredient; wherein when the active pharmaceutical ingredient is acidic, the salt forming substance is a base and the pKa difference between the acidic active pharmaceutical ingredient and the base is greater than 1, typically greater than 2 or preferably greater than 3; or when the active pharmaceutical ingredient is basic, the salt forming substance is an acid and the pKa difference between the basic active pharmaceutical ingredient and the acid is greater than 1, typically greater than 2 or preferably greater than 3,
    Type: Application
    Filed: January 16, 2017
    Publication date: January 24, 2019
    Inventors: Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
  • Publication number: 20180021263
    Abstract: The present invention relates to a method of producing a direct compression tablet composition comprising the step of processing ibuprofen, a hydrophilic polymer, and an inorganic excipient by an extrusion process to produce an extruded composition in which the ibuprofen forms a solid dispersion/solution within the hydrophilic polymer. The invention is particularly useful in preparing oral dissolvable tablets. Also provided are composition comprising an inorganic excipient and ibuprofen within a hydrophilic polymer.
    Type: Application
    Filed: February 9, 2016
    Publication date: January 25, 2018
    Inventors: Dennis Douroumis, Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
  • Publication number: 20180015040
    Abstract: A method of producing an extruded, powdered/granulated composition comprising an active pharmaceutical ingredient (API), by the steps of providing an API and a porous inorganic excipient, and processing them by an extrusion process to directly produce an extruded, powdered/granulated composition wherein the API is at least partially absorbed within the pores of the inorganic excipient. In preferred embodiments, the API is melted, or solubilised in a solubilizer.
    Type: Application
    Filed: February 9, 2016
    Publication date: January 18, 2018
    Inventors: Dennis Douroumis, Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
  • Publication number: 20140312475
    Abstract: A die having multiple sets of contact pads, with each such set having two or more contact pads distributed over the die and electrically interconnected using a respective electrical intra-die path to enable die reuse in a manner that causes electrical inter-die buses to be relatively short in length. Each electrical intra-die path can optionally include one or more respective buffer circuits configured to reduce degradation of the various signals that are being shared by the reused dies. In some embodiments, multiple reused dies can be arranged in a linear or two-dimensional array on an interposer or on the package substrate and packaged together with one or more non-reused dies in a single integrated-circuit package.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 23, 2014
    Applicant: LSI CORPORATION
    Inventors: Anwar Ali, Gokulnath S. Sulur, Tauman T. Lau
  • Publication number: 20130154109
    Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, John W. Osenbach, Anwar Ali, Donald E. Hawk, Robert J. Madge
  • Patent number: 8350375
    Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: January 8, 2013
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Kalyan Doddapaneni, Wilson Leung
  • Patent number: 8151237
    Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 3, 2012
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Julie Beatty, Kalyan Doddapaneni
  • Patent number: 8115321
    Abstract: An integrated circuit includes a number of probe pads arranged in a staggered manner in a core region of the integrated circuit and a number of bond pads in an Input/Output (I/O) region surrounding the core region. The core region includes logic circuitry therein, and the I/O region is configured to enable the core region to communicate with one or more external circuit(s) through the number of bond pads. The integrated circuit also includes a die metal interconnect separating a bond pad area in the I/O region from a probe pad area in the core region. A dimension of the die metal interconnect and/or a position of the die metal interconnect between the probe pad area and the bond pad area is variable.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 14, 2012
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Kalyan Doddapaneni, Gokulnath Sulur, Wilson Leung, Tauman T Lau
  • Patent number: 7863716
    Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: January 4, 2011
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Tauman T Lau, Kalyan Doddapaneni
  • Publication number: 20100276816
    Abstract: Disclosed are a system and method of separate probe and bond regions of an integrated circuit (IC). An IC, an I/O region adjacent to the core region to enable the core region, and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area outside the I/O region of the IC are disclosed. The die metal interconnect may have a length that is greater than the bond pad area length and/or the probe pad area length, and a width that is less than the bond pad area width and/or the probe pad area width. An in-front staggering technique may be used at a die corner of the IC to maintain the bond pad area in the I/O region, and a side staggering technique may be used at the die corner of the IC to maintain the bond pad area in the I/O region.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Inventors: ANWAR ALI, Kalyan Doddapaneni, Gokulnath Sulur, Wilson Leung, Tauman T. Lau
  • Patent number: 7737564
    Abstract: A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the input/output device. The bond pad is then coupled to the input/output device with an interconnect structure. The method for electrically coupling the bond pad to the input/output device allows the customer to configure the power and ground pad counts after the slice is created.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: June 15, 2010
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Tauman T. Lau, Kalyan Doddapaneni
  • Publication number: 20090321897
    Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.
    Type: Application
    Filed: July 23, 2009
    Publication date: December 31, 2009
    Inventors: Anwar Ali, Tauman T. Lau, Kalyan Doddapaneni
  • Publication number: 20090283904
    Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.
    Type: Application
    Filed: May 15, 2008
    Publication date: November 19, 2009
    Applicant: LSI LOGIC CORPORATION
    Inventors: Anwar Ali, Kalyan Doddapaneni, Wilson Leung
  • Patent number: 7569472
    Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: August 4, 2009
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Tauman T Lau, Kalyan Doddapaneni
  • Patent number: 7554133
    Abstract: An integrated circuit with a monolithic semiconducting substrate formed in a chip, where the chip has a peripheral edge, a backside, and an opposing top on which circuitry is formed. A first ring of bonding pads is formed along at least a portion of the peripheral edge. At least one of the bonding pads is configured as a power pad, and at least one of the bonding pads is configured as a ground pad. An intermediate power bus is disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. An intermediate ground bus is also disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. A power pad wire forms an exclusive electrical connection between the power pad and the intermediate power bus. A ground pad wire forms an exclusive electrical connection between the ground pad and the intermediate ground bus.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: June 30, 2009
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Nenad Miladinovic, Kalyan Doddapaneni
  • Publication number: 20090160475
    Abstract: An apparatus and method for reducing the number of package pins in a chip package which must be budgeted for test purposes. In one embodiment, the invention achieves this by housing test balls in the depopulated center of a package ball array. The test balls are used to test a chip package prior to connection with a printed wiring board (PWB)/printed circuit board (PCB). After tests are completed, and when the chip package is connected to a PWB/PCB, the test balls may be left electrically isolated and unconnected. In another embodiment, the test balls are located in previously unused interstitial sites in a package ball array.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Inventors: Anwar Ali, Thinh Tran, Wilson Choi
  • Publication number: 20080320432
    Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
    Type: Application
    Filed: August 22, 2008
    Publication date: December 25, 2008
    Inventors: Anwar Ali, Julie Beatty, Kalyan Doddapaneni
  • Patent number: 7430730
    Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: September 30, 2008
    Assignee: LSI Corporation
    Inventors: Anwar Ali, Julie Beatty, Kalyan Doddapaneni
  • Publication number: 20080099905
    Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Inventors: Anwar Ali, Tauman T. Lau, Kalyan Doddapaneni
  • Patent number: 7328417
    Abstract: A computer-implemented method for creating slotted metal structures in a semiconductor design is disclosed. Aspects of the present invention include providing a library of different types of pre-slotted building block elements. Thereafter, during chip design, a plurality of the elements are selected from the library and placed in the design in abutment to form a composite slotted metal structure.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: February 5, 2008
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Tauman T. Lau, Kalyan Doddapaneni