Patents by Inventor Anwar Ali

Anwar Ali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6704918
    Abstract: A technique is described for enabling routing of metallisation wires over sensitive cells of an integrated circuit by means of a global router after the cell circuits have been designed. At least one cell includes dedicated route paths (32, 36, 40, 46) as part of the cell design. The paths may include alternative paths (32 and 36), and concurrently usable paths (40 and 46). By including the routes as part of the cell design, the subsequent problems of a global routing tool routing wires over sensitive areas of the cell can be avoided, and the number of wire routes can be controlled. The global router operates by detecting whether dedicated routes are provided and, if so, identifying the entry/exit points for routes to be used.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: March 9, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Virendra Patel
  • Publication number: 20040043656
    Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 4, 2004
    Inventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau
  • Patent number: 6683476
    Abstract: An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: January 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Tauman T. Lau, Max M. Yeung
  • Patent number: 6671865
    Abstract: An input/output array of an integrated circuit comprises concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group having x1 number of input/output devices. Each peripheral input/output tile includes x1 number of signal contacts for coupling signals to corresponding ones of the x1 number of input/output devices, y1 number of input/output driver voltage contacts for coupling a source voltage to drivers of the x1 number of input/output devices, and z1 number of ground contacts. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: December 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Farshad Ghahghahi, Edwin M. Fulcher
  • Patent number: 6657870
    Abstract: A power distribution system for distributing external power across a die is disclosed, wherein the die has horizontal and vertical centerlines. The system and method include providing a power mesh that includes a plurality of V-shaped trunks patterned as concentric diagonal trunks extending from the horizontal and vertical centerlines of the die towards the periphery of the die.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: December 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Benjamin Mbouombouo, Max Yeung
  • Publication number: 20030210076
    Abstract: An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Inventors: Anwar Ali, Tauman T. Lau, Max M. Yeung
  • Publication number: 20030209731
    Abstract: A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value. In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Inventors: Anwar Ali, Tauman T. Lau, Max M. Yeung, Ken Nguyen, Wei Huang
  • Publication number: 20030209797
    Abstract: A packaged circuit with VDDcore contacts in first known positions and VSScore contacts in second known positions. A VDDcore mesh layer is fabricated with traces, and a VSScore mesh layer is fabricated with traces. A redistribution layer is disposed adjacent the integrated circuit, and overlies the VDDcore mesh layer and the VSScore mesh layer. First contacts in the redistribution layer are positioned in alignment with the first known positions, to make electrical connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second known positions, to make electrical connections between the redistribution layer and the VSScore contacts. First electrically conductive vias are positioned in alignment with the first known positions, to make electrical connections between the first contacts and the VDD mesh layer, without using a VDDcore bus that extends substantially across the redistribution layer.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Inventors: Anwar Ali, Ken Nguyen, Max M. Yeung
  • Patent number: 6591410
    Abstract: A method for making a bump and trace layout for an integrated circuit die includes the step of replicating a routing tile having a first column of I/O pads and a second column of I/O pads wherein the first column is offset from the second column so that the I/O pads of the first column are interleaved between the I/O pads of the second column.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: July 8, 2003
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Mike Teh-An Liang, Bing Yi