Abstract: Various integrated circuits (ICs) are provided. One IC includes bonding pads and an input output (I/O) region surrounding a core region. The I/O region includes I/O cells having a width approximately equal to or less than a width of the bonding pads. The IC also includes core logic arranged within the I/O region. Another IC includes four rows of bonding pads. Each row is arranged parallel to a different side of a core region. I/O sub-regions are arranged proximate each side of the core region. Each I/O sub-region includes I/O cells and core logic. An additional IC includes a first I/O region surrounding a core region and a second I/O region surrounding the first I/O region. The IC also includes bonding pads arranged outside of I/O cells in the first and second I/O regions. A width of the I/O cells is approximately equal to a pitch of the bonding pads.

Abstract: A packaged circuit with VDDcore contacts in first positions and VSScore contacts in second positions. A redistribution layer is adjacent the integrated circuit, and overlies VDDcore and VSScore mesh layers. First contacts in the redistribution layer are positioned in alignment with the first positions, to make connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second positions, to make connections between the redistribution layer and the VSScore contacts. First vias are positioned in alignment with the first positions, to make connections between the first contacts and the VDD mesh layer. The traces of the VDD mesh layer are positioned in alignment with the first positions. Second vias are positioned in alignment with the second positions to make connections between the second contacts and the VSS mesh layer. The traces of the VSS mesh layer are positioned in alignment with the second positions.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: An integrated circuit is provided which includes at a first, a second, or a third row of bonding pads. A plurality of trace conductors is provided to route the signal of each bonding pad to an I/O ring and/or a core. The trace conductors of different metal widths are configured on a separate and distinct metal layers such that routing may be done above or below the bonding pad rows and other trace conductors. A plurality of vias is provided to connect between the different metal layers. This allows multiple rows of bonding pads to be arranged on the perimeters of the core without having to compromise for small pitch distances or longer routing paths.

Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Abstract: A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value. In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs.

Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.

Abstract: A technique is described for enabling routing of metallisation wires over sensitive cells of an integrated circuit by means of a global router after the cell circuits have been designed. At least one cell includes dedicated route paths (32, 36, 40, 46) as part of the cell design. The paths may include alternative paths (32 and 36), and concurrently usable paths (40 and 46). By including the routes as part of the cell design, the subsequent problems of a global routing tool routing wires over sensitive areas of the cell can be avoided, and the number of wire routes can be controlled. The global router operates by detecting whether dedicated routes are provided and, if so, identifying the entry/exit points for routes to be used.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.

Abstract: An input/output array of an integrated circuit comprises concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group having x1 number of input/output devices. Each peripheral input/output tile includes x1 number of signal contacts for coupling signals to corresponding ones of the x1 number of input/output devices, y1 number of input/output driver voltage contacts for coupling a source voltage to drivers of the x1 number of input/output devices, and z1 number of ground contacts. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one.

Abstract: A power distribution system for distributing external power across a die is disclosed, wherein the die has horizontal and vertical centerlines. The system and method include providing a power mesh that includes a plurality of V-shaped trunks patterned as concentric diagonal trunks extending from the horizontal and vertical centerlines of the die towards the periphery of the die.

Abstract: A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value. In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs.

Abstract: An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.

Abstract: A packaged circuit with VDDcore contacts in first known positions and VSScore contacts in second known positions. A VDDcore mesh layer is fabricated with traces, and a VSScore mesh layer is fabricated with traces. A redistribution layer is disposed adjacent the integrated circuit, and overlies the VDDcore mesh layer and the VSScore mesh layer. First contacts in the redistribution layer are positioned in alignment with the first known positions, to make electrical connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second known positions, to make electrical connections between the redistribution layer and the VSScore contacts. First electrically conductive vias are positioned in alignment with the first known positions, to make electrical connections between the first contacts and the VDD mesh layer, without using a VDDcore bus that extends substantially across the redistribution layer.

Abstract: A method for making a bump and trace layout for an integrated circuit die includes the step of replicating a routing tile having a first column of I/O pads and a second column of I/O pads wherein the first column is offset from the second column so that the I/O pads of the first column are interleaved between the I/O pads of the second column.